By Dr. Phil Garrou, Contributing Editor
While all readers of IFTLE know that advances in chip packaging have been proceeding at a rapid rate at the same time as front end IC advances are becoming harder and harder to achieve, access to these advanced technologies are difficult if you are not one of the large volume players. So, if you are a low volume supplier to the DoD or a custom supplier to smaller companies with low volume requirements you will have trouble finding someone willing and capable of doing business with you in advanced packaging and interconnect. Note, I’m not talking about accessing 3DIC with TSV, I’m talking wafer level packaging including bumping, RDL, copper pillar bump etc. Try going to Amkor, ASE, TSMC or Global Foundries if you need a 100 wafer or 25 wafer order filled.
The response you get will be “No, thanks…nothing personal, you understand… it’s just a business decision.”
Now some of you may say “wait a minute…I know that Xilinx does 2.5D for FPGAs at TSMC and those are low volume products”…You are correct…but that’s for Xilinx…and the rest of you are not Xilinx.
Lets take a break from ECTC coverage to look at an under the radar advanced packaging option if your volumes don’t allow you to access the top tier foundries and assembly houses.
Raytek Semiconductor was formed in April 2016 in Hsinchu Taiwan by packaging veterans Johnson Tai and Dyi Chung (DC) Hu to service customers’ needs specifically in wafer level packaging. Raytek is tooled for both 300 and 200mm wafers. Beside silicon , their line can also process glass and ceramic wafers. Raytek also have a separate 150/100mm manufacture line to process GaN and other non silicon wafers.
Current clean room space is 1677 sq meters with phase 2 additional space of 1582 sq meters coming on line as required. Process areas are class 100. Current wafer capacity is 12,000 wafers/mo.
Since setting up the company two years ago, they claim ca. 100 customers products have been designed with a 100% passing rate after function evaluation and reliability test.
Raytek WLP services include:
– RDL: Cu RDL & Cu/Ni/Au RDL
– Bump: Cu Pillar Bump & Lead Free Bump
– WLCSP: Plated Bump
– WLCSP: Ball Drop (Q4/2018)
– Cu/Ni/Au RDL, Thick Cu UBM/RDL
– Cu/Ni/Au RDL for Au or Cu wire bonding
– RDL L/S = 5/5um and Multi-layers RDL (up to 4PI/3Metal)
– Cu RDL for GaN wafers
-Low or high temperature cure dielectrics can be selected depending on requirements, 4-10um std.
-Applied in specialty memory , high power IC
– Bump ( Lead free bump, Cu pillar bump )
– Lead free solder and low alpha emission lead free solder can be plated
– Copper pillar pitch is 40µm, with max height 135um
-Applied in ASIC, Controller, Power, RFIC, High end memory devices (8GDDR4,HBM)
– One Stop Service
– Backside Grinding, Backside Metal, Dicing, Tape & Reel done in house
So, if you’re in need of these types of services check out Raytek.
So for all the latest in Advanced Packaging, stay linked to IFTLE…