Author Archives: sdavis

IFTLE 370 3D-ASIP Part 3: Bonding and Assembly in HBM Memory Stacks

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 14th annual 3DASIP Conference.


Tom Strothmann of K&S discussed the requirements for HBM Memory Stacking. High Bandwidth Memory (HBM 1,2) are currently assembled using C2W compression bonding. Production is mostly done by memory suppliers as opposed to OSATS. HBM 3 is projected for 2019.

K&S 1

There are two prominent stacked die process flows:

    • TC-CUF (Thermocompression with Capillary Underfill)
      • Die by die stacked using TCB
      • Die stack tacked followed by mass reflow
    • TC-NCF (Thermocompression with Non-Conductive Film)
      • Stacked die by die using TCB
      • Die stack tacked followed by Collective Bond
      • Die stack tacked followed by Gang Bond

Cost reduction has focused on units/hr for the TCB process:

    • Bondhead temperature ramp speed
    • Target and die material handling systems
    • Number of bondheads and accuracy requirements

Tacking has the potential to move machine UPH from 1700 to 3500 for a 4 die stacked process using NCF if a separate gang process is used.

K&S 3


TSV Die Stress and Warpage

  • Silicon thinned to 50 microns during the via reveal process then has backside dielectrics and UBM applied
  • Imbalanced stress resulting from the dielectrics, metals and pillars on the front of the wafer as compared to the back of the wafer causes warpage in the thinned silicon wafer
  • Stress remains after dicing, resulting in die bowing that can be as much as 40um in a 9x9mm die

TCB with CUF Process

  • TC-CUF processes have been used for stacked die production in HVM. Flux dip before placement followed by capillary underfill is a mature process.
  • Typically lower throughput because the flux dip must be done below 100ºC to avoid premature activation of the flux. UPH >1000 is still possible during bonding with a dual head machine.
  • TC-CUF die stacks have a narrow process window due to thin die warpage. Single die can be held flat during the bonding process , the next die in the stack does not. Heat is conducted through the thin silicon and Cu pillars into the die below, causng solder remelt and relaxation to original warped shape resulting in BLT variation. Since the top die is still held flat, this can create inconsistent bondline thickness throughout the stack.

TCB with NCF (non conductive film)

  • NCF has the benefit of locking the BLT during the bonding process to enable a “flat die” process and more consistent bond lines
  • TCB process can be optimized independent of die stack position
  • Potential to remelt a lower die and change BLT is removed, enabling better process capability
  • But…high forces may be required for bonding some layers based on die size and pillar count

As shown below the thickness of the NCF must be exact or the interface will suffer from particle entrapment or voiding.

K&S 2

Strothmann also offered the following opinions on alternative bonding approaches:

  • Cu-Cu bonding is an area of active development work but is less likely to be applied to memory stacking in the near future
  • Direct (hybrid) bonding of chip to wafer is unlikely for memory stacking

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 369 Samsung HBM2; Ultra Fine Pitch Interconnect; Thin Die Pick and Place

By Dr. Phil Garrou, Contributing Editor

First introduced in June 2016, the Samsung HBM2 consists of eight 8Gb HBM2 dies and a buffer die at the bottom of the stack, vertically interconnected by TSVs and µbumps. With each die containing over 5,000 TSVs, a single Samsung 8GB HBM2 package has over 40,000 TSVs. Including spares TSVs ensures high performance, by enabling data paths to be switched to different TSVs when a delay in data transmission occurs. The HBM2 is also designed to prevent overheating beyond certain temperature to guarantee high reliability. The HBM2 reports a 256GB/s data transmission bandwidth, offering more than an 8X increase over a 32GB/s GDDR5 DRAM chip. With capacity double that of 4GB HBM2, the 8GB solution contributes greatly to improving system performance and energy efficiency, offering ideal upgrades to data-intensive, high-end computing (HPC) applications that deal with machine learning and graphics processing .

Last week Samsung announced that it has started mass production of its 2nd-generation 8-gigabyte (GB) High Bandwidth Memory-2 (HBM2) with the fastest data transmission speed on the market today.[link] Dubbed “Aquabolt”, it is claimed to be the industry’s first HBM2 to deliver a 2.4 gigabits-per-second (Gbps) data transfer speed per pin, at 1.2V for the supercomputing and the graphics card market.

This performance is reportedly 50% greater than the 1st-generation 8GB HBM2 package with its 1.6Gbps pin speed at 1.2V and 2.0Gbps at 1.35V.

A single Samsung 8GB HBM2 package will offer a 307 GBps data bandwidth, achieving 9.6 times faster data transmission than an 8 gigabit (Gb) GDDR5 chip, which provides a 32GBps data bandwidth. Using four of the new HBM2 packages in a system will enable a 1.2 terabytes-per-second (TBps) bandwidth.

In addition, Samsung increased the number of thermal bumps between the HBM2 dies, enabling better thermal control in each package. The new HBM2 also includes an additional protective layer at the bottom, which increases the package’s overall physical strength.

Samsung HBM2


Continuing our look at the presentations at the 14 3D ASIP Conference.

Micross – Ultra Fine Pitch Interconnect

Matt Lueck of Micross gave a presentation on their Ultra fine pith interconnect technologies that are being used in their Northrup Grumman (NGC) DARPA CHIPS program discussed in IFTLE 367 [link].

Fine pitch (< 80 um), Cu pillar thermo-compression bonding (TCB) has been widely adopted for advanced packaging of stacked memory and many other applications. Major foundries and assembly houses are offering Cu pillar down to 30 – 50µm pitch with 20 – 30µm pitch in development. Availability of fine pitch Cu pillar bumping from foundries and OSATs are limited to high volume customers and off-shore processing.

Micross has been developing fine pitch technologies over the years under their previous ownership ( Microelectronic Consortium of NC (MCNC) and Research Triangle Institute (RTI). They re positioning themselves as a source for prototype and small volume production of such ultra high pitch interconnect.

They have used 10µm pitch Cu/Sn – Cu bonding in multiple programs since 2007 such as large area array detector applications. They report that such interconnect have shown proven reliability, even for heterogeneous integration with CTE mismatch issues.

  • For next generation area array imaging applications, sub-10 µm pitch electrical interconnects are desired between detector chip and ROIC
  • A process for the fabrication and bonding of 5 µm pitch Cu-Cu interconnects was demonstrated
  • I-V curves indicate ohmic behavior of interconnect chains
  • Leakage current measurements indicate > 100 GΩ isolation between adjacent channels of interconnects
  • Demonstrated high yield on 1280 x 1024 array sample

Micross 1

Working with NGC they are developing 4 – 10µm pitch gold-gold bonding technology. The evaporated gold bumps show RMS roughness of 3.7-3.9nm.

micross 2

BESI- Thin Die Pick and Place

Stefan Behler of Besi discussed “How to peel Ultra this dies from Wafer tape”

Behler describes 4 key properties as shown below:


(1) Wafer foil peel force depends on the foil type and the peel speed as shown in table below.

besi 2

(2) edge peel force depends on the dicing method

(3) Bending stress depends on the Ejector type with thinned die resulting in more bending stress.

besi 3


(4) die strength appears (measured by 3 point bending test) is almost independent of thickness but is dependent on :

  • surface (active structure)
  • backside (grinding, polishing…)
  • edges (dicing)

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 368 IMAPS addresses the Chip-Package Interaction (CPI)

By Dr. Phil Garrou, Contributing Editor

This week, I am interrupting our look at the 2017 3D-ASIP conference to take a look at consolidation in the equipment industry and the recent issue of IMAPS Advancing Microelectronics magazine.

Equipment Consolidation

IFTLE has explained many times that a sure sign of industry segment maturity is when the 3 top players have a combined > 80% market share. The best examples of this currently are hard disk drives and DRAM memory.

The latest data on the equipment industry market shares points to this segment being very close [link] . Had the TEL/ AMAT merger gone through, the industry truly would have reached the definition of maturity. I would be looking for attempts at other combinations in this segment to be coming soon.


Chip Package Interaction

Urmi Ray, VP of Technology for STATS ChipPAC (JCET) has edited a special edition on the chip-package interaction, which is definitely worth a read [Advancing Microelectronics, Nov/Dec 2017, V44, No 6.][Link]

As most of you know, CPI is the interaction between the semiconductor package stresses and the semiconductor device. Package stresses are caused by thermal, mechanical and chemical mechanisms. CPI contributes to various failure modes during package assembly and field life. The emergence of both fan in and fan out wafer level packaging, while delivering unparalleled form factor and cost improvements by eliminating the package substrate, has resulted in loss of a buffer layer between the chip and PCB resulting in additional stresses being transmitted to the die surface during SMT assembly.


Zhao and co-workers at Qualcomm discussed the “Electrical Chip- Board Interaction (e-CBI) of Wafer Level Packaging Technology”.

The industry is clearly moving packaging technology toward WLP and Fan-Out WLP to reduce packaging cost and form factor. One of the key dif­ferences between Flip Chip CSP (FCCSP) and WLP/FOWLP is the absence of a package substrate in the latter packaging options. For e-CPI in FCCSP, the package substrate isolates the chip from the PCB. Without the package substrate, the silicon die in WLP/FOWLP directly inter­acts with the PCB board. The mediation of the board stresses by the packaging substrate is now gone and one must evaluate the risk of direct PCB stress on the chip, i.e. electrical chip-board interaction (e-CBI). For WLP and FOWLP, e-CBI can be signifi­cant.

For example, they point to the fact that visual in­spection of FOWLP reveals dimple patterns on the backside of the parts after board level underfill which correlate with the pat­terns of BGA depopulation. In the absence of the mechanical support from BGA solder balls in the depopulated areas, the board level underfill shrinkage pulls the thin silicon die to­wards PCB. FEA models have verified this phe­nomenon and reproduced similar “dimples”. Since the silicon die bends toward PCB in the BGA depopulated regions, this infers that tensile stress is being created on active silicon surface.

qualcomm 1



Ivor Barber and co-workers discussed “14nm Chip Package Interaction Technology Development.”

With the implementation of extreme low K (ELK) porous dielectric materials (k < 2.5) into the back end of line (BEOL) to reduce the in­terconnect capacitance and cross-talk noise and enhance circuit performance, the lower mechanical strength of the ELK, along with increased die size, difference in effective coefficient of thermal expansion (CTE) between die and substrate, and the use of higher stiffness lead free solder increasingly contribute towards ELK layer cracking. Chip package interaction (CPI) be­came one of the critical reliability issues that needed to be addressed to avoid electrical or mechanical failure in products.

In order to evaluate CPI risk and reliability concerns from a technology point of view, they developed a CPI test vehicle (TV) which must include the same BEOL stacks, same ELK ma­terial, same BEOL process, same bump technology, same substrate technology, same assembly process for the pro­duction of the same Si node. In their 14nm CPI development, a 14nm TV with die size of 21×21 mm2 with 140um bump pitch of SnAg bump has been selected. 40×40 mm2 substrate has been used in our CPI technolo­gy qualification. JEDEC standard tests (Precon, UBHAST, TCJ, MSL, and HTS) were used as criteria for the CPI tech­nology qualification.

ELK delamination / cracks called “white bumps” are encountered as rigid lead free bumps would transfer more stress to weak ELK layers causing ELK crack underneath the bump. Unlike bare silicon dies, thermal deformation of pack­aged dies can be directly coupled to Cu/low-k or ELK interconnects, inducing very high local stresses to drive fracture and delamination. ILD delamination is caused due to dicing defects like micro-cracks and poor adhesion or mechanical strength of low-k/ELK dielectric materials under the thermal load of the processes like flip-chip as­sembly process or thermal cycling tests.


In order to improve the CPI margin, studies have examined passivation thickness, polyimide thickness, under bump metallization, CTE of substrate, and FBEOL. Simulation and DOE have shown that by using thicker Aluminum terminal metal and two layers of passivation, the CPI risk reduced significantly. So foundries have now implemented this dual pas­sivation layer with Al terminal metal to enhance CPI reli­ability.


Simulation has shown that ELK stress are reduced with reduced bump pitch.

The fracture toughness of low-k/ELK dielectrics vs SiO2, is substantially reduced and is significantly lower than that of Si. It is thus much easier to induce defects like micro-cracks during dicing. Those tiny cracks can develop and propagate into the active die area and cause failure un­der thermal-mechanical stress. One approach to prevent cracking at the die edge or die corner is to apply patterned metal structures called crack stop around the perimeter, especially reinforced at the die corners. They found that double wall crack stop was necessary for products with large die size to provide protection for the dicing defects.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 367 CIS Consolidation; DARPA CHIPS Headlines 14th 3D-ASIP Conf.

By Dr. Phil Garrou, Contributing Editor

Consolidation in CIS Market

Remembering our IFTLE rule [ see IFTLE 241, “Simply Obeying the Laws of Economics”] that maturing markets have 3 players with > 85% of market share, we note that Gartner Assoc. has reported that the top 5 vendors accounted for 88.9% of global CIS revenue in 2016 and the top 3 companies have 78.9% of the market, up from 77.1% in 2015 so we are getting close… [link]

GArtner 1


Teledyne / DALSA

Invensas (Experi) has announced technology transfer of its Direct Bond Interconnect (DBI) to Teledyne DALSA. This capability enables Teledyne DALSA to deliver next-generation image sensors to customers in the automotive, IoT and consumer electronics markets. Invensas and Teledyne DALSA announced the signing of a development license in February 2017. All of the major image sensor players appear to be adopting this image sensor stacking technology.

Chip Stacking for Image Sensors

Ray Fontaine at TechInsights has this to say about image sensor technology in 2017 “Chip stacking (image sensor + image signal processor) for image sensors remains an enabling technology for improved camera performance, and this year we documented Sony’s first-generation TSV-based three die stack (now adding a DRAM) in mass production. For two-die stacks, we still primarily see TSV-based chip-to-chip interconnect, although Sony has been using direct bond interconnects (Cu-Cu hybrid bonding, or DBI) since early 2016. We recently saw OmniVision and foundry partner TSMC join the hybrid bonding club and claim the new world record, based on TechInsights’ findings, of 1.8 µm diameter, 3.7 µm pitch DBI pads.” [link]


The 14th annual 3D ASIP conference, in early December, deviated somewhat from its traditional focus on 3DIC content to cover ancillary and complimentary technologies. Below we see incoming IMAPS President Ron Huemoeller presenting plaques to Gen Chair Garrou and Tech Chairs Scannell and Koyanagi.

Gen Chairs



DARPA has a long history if chip integration as is depicted in the slide below showing DARPA programs and their acronyms.



IFTLE has had extensive discussions on the 2017 DARPA CHIPS program. [see IFTLE 323 “The New DARPA Program “CHIPS”…”].

In his plenary presentation, DARPA program Mgr. Dan Green pointed out that the CHIPS goal is to develop design tools, integration standards, and IP blocks required to demonstrate modular electronic systems that can leverage the best of DoD and commercial designs and technology. Particular emphasis is being placed on trying to develop a technology infrastructure that can be adopted by both the aerospace infrastructure and the commercial infrastructure.


The CHIPS grants are led, as shown below, by Boeing, Intel, Lockheed Martin, Northrup Grumman and the Univ of Michigan.

darpa 3

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 366 IWLPC Part 3; LED WLP & IMEC & Experi Hybrid Wafer Bonding

By Dr. Phil Garrou, Contributing Editor

IZM Fraunhoffer TU Berlin and Osram

Tanja Braun of IZM Fraunhoffer discussed “Fan-out and Panel level technology for Advanced LED Packaging.”

The ongoing miniaturization in LED chip size and thickness down to 200 μm and below requires adapted chip handling and assembly. Innovative solutions are needed to electrically connect top and bottom contacts of the LED guaranteeing at the same time a sufficient overall thermal concept. Polymer based package solutions need to consider the aging/yellowing of the polymers on constant exposure to intense light. High volume and low cost solutions are required.

A blue LED with an area of 1×1 mm² and a thickness of 120 μm was chosen for package development. The LED has one contact pad on the topside and needs an additional electrical connection to the backside. The overall concept for the SMD compatible single LED package is shown below.


Package size was designed to 1.6×1.6 mm² allowing the integration of a through mold via (TMV) with 100 μm diameter routing the contact from the topside to the SMD compatible pads on the package backside. Package mold thickness is 300 μm resulting in a mold layer of 180 μm on the backside of the LED. The backside of the LED is connected by a blind via with a diameter of 250 μm. The process flow is shown below:


Compression molding is used for reconfigured wafer encapsulation. Recent developments now allow panel molding for sizes up to 600×600 mm². Compression molding evaluation within this study has been performed on 200 mm with a wafer level machine from TOWA and with a large area panel mold machine from APIC Yamada using a tooling with a cavity size of 457 x 305 mm². For the LED package development a liquid black epoxy molding compound (EMC) has been selected with a filler particle top cut of 25μm. Material with small maximum filler particle size has been chosen to allow laser through mold and blind via drilling with precise geometries and smooth via walls.

Die shifting is one of the key challenges during “Mold first” FOWLP. Due to the different thermo-mechanical properties of carrier, thermo-release tape and epoxy molding compound dies move such that the die position is shifted with respect to placement position after cooling down from compression molding. This effect is also influenced by the chemical shrinkage of the molding compound. Die shifting can be overcome by using a fast AOI (automated optical inspection) in combination with maskless processing for die connection and rewiring. This would give the opportunity to tolerate larger die misplacement by adapting the layout to the real die position.

Vias to the top side ad backside are shown below.



Cavaco of IMEC discussed heir results on “Hybrd Copper Dielectric Direct Bonding of 200mm CMOS Wafers with 5 Meta Layers…” where IMEC reports wafer level electrical data and reliability testing results for 200-mm wafer to wafer hybrid copper to dielectric aligned bonding on short loop wafers which consist of five backend of line (BEOL) metal levels using silicon carbon nitride (SiCN) as dielectric. The fabricated 200-mm wafer pairs are representative of a real CMOS device structure as they are processed with five metal levels per test wafer in a 130-nm copper BEOL CMOS technology.

In the wafer to wafer hybrid bonding process, two substrates are connected simultaneously by a copper to copper metal bonding and by an inter layer dielectric (ILD) oxide bonding. Some of the main issues inherent to the hybrid bonding process are: the profile of the copper pads after copper chemical-mechanical-planarization (CMP); the oxide erosion; the used surface treatment before bonding; the wafer to wafer bonding alignment accuracy; the contact integrity; the contact reliability; and manufacturing yield issues.

The full bonding sequence essentially comprises a wet clean module, a plasma module for surface activation and a bonding aligner module. A bonding accuracy below 1μm can be achieved by using dedicated alignment keys on both sides of the wafers. Bonding misalignment on the X direction was of the order of 0.7μm. Afterwards, the wafers were brought into proximity and dielectric bonding took place. Subsequently, copper to copper bonds are formed during a post-bonding anneal step.

SiCN was chosen as the dielectric layer(a) because SiCN is known to have a higher bonding strength when compared to SiOx, or SiN and (b) because SiCN can act as a barrier against metal diffusion into the dielectric, which can take place when using SiOx in a hybrid bonding process that comprises copper line patterns.

To confine the copper bonding pad dishing/protrusion to values below 10 nm, a strict process control of the CMP step is required on all wafers.

IMEC 1-2

In this study, both HTS and TC reliability testing were performed at wafer level. More specifically, TC testing consisted of up to 1000 temperature cycles, of one hour each, from -40 °C to +125 °C. HTS testing consisted of storing the wafers, in a nitrogen environment, up to 1000 hours at +125 °C. Zero-yield loss observed at the end of both TC or HTS reliability testing.

Xperi (Ziptronix)

Gao and co-workers from Xperi discussed their studies on the “Development of Hybrid Bond Interconenct Tech for D2W and D2D Applications”

We have discussed previously the acquisition by Xperi (Tessera) of Ziptronix and their DBI bonding process [see IFTLE 253, “China Inc Seeks to Acquire GF; Tessera Acquires Ziptronix; Tezzaron 8 layer 3DIC “ (link)]

This DBI (hybrid bonding) technology has been licensed and widely adopted by players in the CMOS imaging sensor industry such as Sony and Omnivision [see IFTLE 325, “ Omnivision takes Ziptronix License…” (link)]

To the best of my knowledge al of the CMOS image sensor work is being done on 200mm wafers , i.e W2W. Rumor has it that the process is much more difficult when trying to do D2W or D2D bonding. Attempting to resolve this issue and expand the use of the process in their applications, Xperi has undertaken a study of the D2W process looking to compare it to the more standard TCB (thermos compression bonding).

Obviously aiming at the stacked memory business, their test structures consisted of a host wafer designed to mimic the logic controller in a HBM stack. The fig below shows an illustration of four dies stacked on top of a host wafer. Daisy chain coverage includes hybrid bonding between the following interfaces: host die to die 1 bottom: die 1 top to die 2 bottom; die 2 top to die 3 bottom; and die 3 top to die 4 bottom. Currently, the stackable die does not have through-silicon vias (TSV). Consequently, electrical testing is limited to the die 1 bottom to host die interface. For next phase of development, TSV will be included to enable electrical testing of all interfaces.

Experi 1

It is desirable to maintain the RMS roughness of silicon oxide on the bonding surface below 0.5nm to facilitate high bond energy between the silicon oxide components of the hybrid bond. A similarly low surface roughness of copper is also desirable (although less critical) to further increase bond energy. In addition, it is desirable to have the Cu surface slightly recessed from the oxide surfaces.

The table below compares the total process time and throughput of a bonder for TCB and hybrid bonding. The hybrid bonding process requires very low contact force. It is essentially a P&P only process. It requires no temperature profile, no pressure control and no dispensing of additional material. On the Toray bonder, they demonstrated that 10s and 1s bonding dwell time shows the same bonding results. On the Datacon bonder, we have demonstrated bonding dwell time of 0.1s. With addition of 0.5s material handling time to each machine, the calculated throughput is 2400 unit per hour (UPH) on the Toray bonder and 6000 UPH on the Datacon bonder.

Compared to TCB, the hybrid bonding requires additional processes for die cleaning, activation and anneal. However, all these processes are carried out in batch and does not limit the throughput of the bonder.

experi 2


Bonds with poor electrical contact appear to be the result of particulate contamination . Such contamination is considerable reduced in a class 100 clean room environment. Optical images of the die stack is shown below.

experi 3

For all the latest in Advanced Packaging Stay, linked to IFTLE…

IFTLE 365 Altera FPGA with HMB2 and EMIB; IWLPC 2017 Part 2

By Dr. Phil Garrou, Contributing Editor

Merry Christmas and Happy New Year to One and All


Intel Altera release Stratix 10 FPGA with HBM2 memory and EMIB connections

Before we continue our coverage of the 2017 IWLPC, I need to make sure everyone has seen the announcement from Intel (Altera) on the availability of the Intel Stratix 10 MX FPGA, their FPGA (field programmable gate array) with integrated HBM2 (High Bandwidth Memory). [link]

Intel 1

The Intel Stratix 10 MX FPGAs, utilizing Intel’s 14 nm FinFET process, reportedly offer up to 10X the memory bandwidth as compared to standard DDR 2400 DIMM standalone memory solutions. In HPC environments, the ability to compress and decompress data before or after mass data movements is paramount. HBM2-based FPGAs can reportedly compress and accelerate larger data movements compared with stand-alone FPGAs.

The Intel Stratix 10 MX FPGA family provides a maximum memory bandwidth of 512 Gb per second through the integrated HBM2. The Intel Stratix 10 MX FPGA family utilizes Intel’s EMIB technology (Embedded Multi-Die Interconnect Bridge) for high density connections. IFTLE thinks this is the first commercial implementation of EMIB technology in the industry.

intel 2

IWLPC part 2


Brubaker and Strothman of KNS discussed the “Application of Infrared Inspection to Thermo-compression bonding and die placement”.

In die placement processes, accurate die placements are required to ensure the formation of functional and reliable electrical interconnections. Verification of accurate die placement can be a challenge for standard flip chip products where there are no patterned features on the backside of die. Cross-sectioning or X-ray inspection can be done, but cross-section inspection requires that samples be epoxy under-filled, ground, polished, and inspected using a microscope. X-ray inspections typically require offline processing with dedicated equipment.

In situ measurement within the die placement equipment itself would be preferable. Typically, die placement machines are equipped with a camera which is utilized for target alignment operating within the visible spectrum. The addition of infrared inspection capability to die placement equipment resolves the limitations presented for in situ visible inspection. Because silicon is transparent to infrared light, an infrared inspection system is able to see through the blank backside of die to detect internal metal patterns. Silicon wafers and die which have been back thinned using a fine grind or polishing process are excellent candidates for infrared inspection. Wafers which were back thinned using coarser mechanical grinding (2000 grit and 1200 grit) yielded lower quality infrared images. The impact of this limitation is believed to be minimal, since most high-end die which require high accuracy placement are evolving to thinner packages which already require fine surface finish to prevent die cracking and wafer warping.

In addition to surface finish, die designs must include features which can be used to generate images with sufficient quality to measure die offsets. In many cases, no special considerations are required in terms of die design. If the absolute best possible placement capability is desired, it is noted that dies which include features optimized for infrared inspection will maximize measurement capability.


Bellman and co-workers from Corning Glass discussed “Temporary Bonding for High Temp Processing of Thin Glass”.

Their “Advanced Lift-off Technology (ALOT)”, is a temporary wafer bonding method for thin glass which reportedly permits subsequent processing over 400C. Fluorocarbon plasmas modify the surface of the glass permitting subsequent controllable van der Waals bonding between a thin glass plates at room temperature. This modification can withstand the vacuum, thermal, wet processing steps of BEOL processing. However, the bond energy between the pair remains low-enough after the thermal processing steps that renders the pair fully detachable.

The ALOT process involves treating a clean hydroxylated glass carrier surface in low-pressure plasma containing CHF3 (or C4F8) and CF4 gases. The CHF3 gas acts as a polymerizing agent and deposits organic fluorocarbon species on the glass carrier while CF4 acts as an etchant and tends to etch away both glass and the organic polymer deposited by CHF3.

In the figure below they plot the bond energy as function of annealing temperature for glass to glass carrier without ALOT treatment (marked as “glass on glass”) and for thin glass bonded to ALOT treated glass carrier corresponding to three initial surface energies (40 mJ/m2, 55 mJ/m2, 72 mJ/m2). The bond energy of untreated glass to glass pair increases exponentially after 200 °C rendering the pair permanently bonded due to covalent bonding. On the other hand, the bond energy of thin glass and ALOT-treated glass carrier pair remains fairly constant at a moderate value up to 400 °C irrespective of the initial surface energy of the glass carrier. This renders the thin glass- glass carrier pair de-bondable after ay post processing which experiences a maximum temperature excursion of ~350-400.

corning 1


Barker and co-workers at SPTS discussed “RC Management for Next Gen PVD UBM/RDL Metallization Schemes”.

Organic materials such as PI or PBO dielectric passivation, epoxy mold compound (EMC), or adhesives for bonded wafers with 2.5D and 3D TSV) have the potential to contaminate under bump metal (UBM) or redistribution layers (RDL) producing a potentially undesirable increase in electrical contact resistance (Rc). With the reduction of UBM/RDL via dimensions in line with device shrinks, contamination effects become more critical.

When placed under vacuum and heated, organics will outgas moisture significantly more than traditional ‘front-end’ dielectrics such as SiN and SiO2. When those same organics are sputter-etched during the subsequent UBM/RDL pre-clean step to remove native oxide from exposed metal contacts, they release volatile carbon by-products from their surfaces. Both moisture and carbon by-product contaminants can react with the cleaned exposed metal pad contacts, forming a layer that increases the contact resistance of overall metallization interconnect scheme produced. The problem is particularly acute with advanced node devices with small contact area dimensions where the contaminant has a proportionally larger impact.

New package schemes such as FOWLP can include wafers that feature singulated die embedded in epoxy mold compound (EMC), and have organic dielectrics surrounding the RDL. These materials present challenges, including moisture absorption, excessive outgassing and a limited tolerance to elevated temperatures. Whereas conventional circuits built on silicon can withstand heat up > 400C and can be degassed rapidly without impacting system throughput, the presence of any EMC, organic dielectrics, or bonding adhesives introduces a lower heat tolerance which can be as low as 120C. Temperatures exceeding these lower thresholds can cause decomposition of the organic based materials, in EMC case; it can lead to excessive wafer warping. Degassing wafers at such low temperatures naturally takes a longer amount of time.

Multi-wafer degas (MWD) technology has emerged as a solution to this problem, enabling many wafers to be degassed at 120C in parallel before being individually transferred to subsequent process steps, without breaking vacuum. Each wafer can spend up to 30 minutes inside the MWD, but because they are processed in parallel, a “dry” wafer is outputted for metal deposition every 60 to 90 seconds, at a rate of between 30 to 50 wafers per hour. This approach increases PVD system throughput by 2-3 times.

If a wafer with organics present isn’t degassed sufficiently prior to pre-clean it can produce high levels of outgassing that affect plasma stability during etch, and film quality (Rc) during subsequent sputter deposition. As the surface of the wafer is etched during the pre-clean step, native oxide is removed from the exposed metal contact, but the ion bombardment damages the surface of the organic passivation, releasing volatile carbon species, which, re-contaminates the metal contacts.

spts 1

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 364 2017 IWLPC Part 1: Advances in Packaging Polymers

By Dr. Phil Garrou, Contributing Editor

Let me start by saying this year’s IWLPC presented what I consider to be the best program in their history. Congrats to the organizing committee for upgrading the technical content of this conference. Collecting and sharing both the presentations and the papers was an added benefit to attendees.

We will first take a look at presentations that described new polymer dielectric advancements.

HD Micro

Matsukawa of HD Micro described their “Low temp curable PI/PBO for Wafer Level Pkging”.

For next generation advanced packaging technologies, the most important requirements for dielectric materials are low temperature curability, high lithographic performance, high chemical resistance, and low warpage. They report on new low temperature (<200⁰C) curable PI and PBO.

Conventional photosensitive PIs and PBOs have required curing temperatures greater than 300ºC to complete cyclization as well as advance polymerization. To formulate low temperature curable materials, they re-designed the polymer backbone in order to enhance cyclization and changed the cross-linker to form a strong network structure even when cured <200⁰C. They presented the following table comparing “conventional PI” (what ever that is ??) to the new generation PI as shown below.

HD 1

Generally positive tone photo-definable materials are composed of a PBO precursor, a photo acid generator, cross-linker etc. Regarding the new positive tone PBO, a suitable photo acid generator and cross-linker combination was selected to increase the resolution while also improving the adhesion to Cu, which has been a significant problem for past generation products. Properties are shown below.

HD 2


Araki of Toray discussed their “Novel Low Temp curable positive tone photo dielectric material with high elongation for panel processing”.

Dielectric materials for redistribution layers (RDL) are one of the most important materials for fan out panel level processing (FOPLP). Toray introduces a low-temperature curable positive-tone photosensitive dielectric material with the high elongation property for fabricating RDL on FOPLP. The high elongation property was achieved by the introduction of flexible molecular skeleton in the base polymer backbone to increase the entanglement of each polymer chain. Cured films showed elongation up to 80%. This positive-tone photosensitive material offers fine pattern (3 um trench and 5 um line and space) with good sensitivity (300 mJ/cm2 (i-line)) and shows high chemical resistance toward resist strippers. Properties of their new PI are shown below.

toray 1

Hitachi Chemical (HC)

Fukuhara of Hitachi Chemical described their “Photo-sensitive Insulation Film for Encapsulation and Embedding” Conventional PoP with flip chips mounted on BGA like substrates is shown below compared to a fan out PoP.

hitachi chem 1-2

In order to make a high density connection between upper and lower packages, it is necessary to form fine pitch through holes on the bottom package. These through hole vias can be formed by laser drilling. HC has developed a laminate photo film which allows encapsulation of the die and subsequent photo formation of the required vias through the film as shown in the process below.

hitachi chem 2-2


Reliability results are show below.

hitachi chem 3

Onozeki of Hitachi Chemical discussed “Wafer Level Packaging Materials and Processes” where he examined the influences of the material properties of temp bond adhesives (TBA) and epoxy mold cmpds (EMC) on the warpage of FO-WLP during the fabrication process by both of the experiments and finite element analysis.

For TBA, it was found that “the deformation of TBA results in relatively free shrinkage of EMC on the support, and Young’s modulus of TBA influences on the warpage most significantly. The small Young’s modulus TBA suppressed the warpage regardless of the support materials”. As for the EMC, “…the low Young’s modulus, low CTE and low Tg are effective to reduce the warpage after post mold curing. The warpage after grinding EMC was smaller than those after post mold cure and there was no big difference in the influence of the mechanical properties”. As for FO-WLP structure, the wide die pitch, thin EMC and thick die are effective to reduce warpage. Especially, the wide die pitch contributes to reduce the warpage. 4 layers re-distribution layer with line and space of 2 and 2 μm was successfully fabricated. The layers were interconnected with small diameter filled Cu vias of 5 μm. The vias were formed in the photosensitive dielectric material. A bias HAST test revealed that this material had enough insulation reliability.


Okamoto from JSR discussed “Fine Pitch Plating Resist for High Density FOWLP”.

For the next generation of high density FO-WLP, RDLs as low as 2um are reportedly required to support more I/O’s and multiple RDL layers. In this situation, RDL plating resists have to provide higher resolution with a wider common depth of focus margin than conventional resists because there are often large topographic gaps between the chip and the mold substrate. The plating resists must also be applicable for various plating solutions under each recommended process condition. JSR describes the development of a resist that has resolution to 0.7um L/S at 5um film thickness and has excellent resistance to various plating solutions.

For all he latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 363 IMAPS 2017 Part 4: DARPA SHIELD; Shinko embedded die for PoP; Rf Interposers

By Dr. Phil Garrou, Contributing Editor

Hope all my readers in the USA had a great Thanksgiving. For those of you around the world, this holiday occurs in late November in the US when families get together for a 4-day weekend. I was with my two sons and my granddaughters Hannah and Madeline (who you have watched growing up ) in Houston and it was great to spend some time together. Younger son Christopher, who is a Chef in Maine, joined us and helped with the cooking activities.



Now let’s finish our look at the 2017 IMAPS Conference.

Northrup Grumman

Under the DARPA/MTO SHIELD program Northrup Grumman led a team of GaTech, Sandia, Kilopass and RFID Global solutions have developed a supply chain traceability and authentication method to protect against counterfeit electronic parts. The solution consists of the incorporation of a 100 x 100 x 20um “chiplet” (they call dielet) fabricated in 14nm CMOS. Authenticity is verified using an Rf probe to energize and communicate with the chiplet. Putting the size of the chiplet into perspective, the pic below shows the chiplet on the head of Lincoln on the back of a penny.

NG 1

The chiplets are manufactured using GlobalFoundries 14nm FinFet technology. The 300mm wafers are thinned and the 20um dicing streets result in ~ 4MM chiplets per wafer. Pick and place of these tiny chiplets is “challenging” but they have developed a technique to insert them into the host packages. Process flow is shown below:

NG 2


Kyozuka of Shinko discussed the “Development of Thinner PoP Base Packages by Die Embedded and RDL Structure.”

PoP structures can achieve thinness by embedding a die (or dies) into a package thus achieing height reduction for devices like APS (application processors). Their “die embedded with RDL” structures are shown in the fig below with design specs.

shinko 1

The process flow is shown in the fig below.

shinko 2

The FC process is done by TCB (thermos-compression bonding) followed by capillary underfill . After die mounting the cover layer of laminate is vacuum laminated and vias are laser drilled to make connection between the substrate and the top RDL. Expected issues with warpage were controlled by controlling layer thicknesses and copper density on the layers.

Via formation included laser drilling, desmear, electroless and electrolytic copper plating. Vias were tested under condition B (-55 to 125◦C) with 75 and 100um visa passed such testing.


Bart Vereecke of IMEC discussed “Investigation of wafer level packaging schemes for 3D Rf interposer multi-chip module”. The fig below schematically shows the structure with a GaAs MMIC mounted on the silicon interposer. The interposer consists of two metal levels sandwiched around a MIM cap layer. A Cu/Ni/Sn seal ring is designed in for bonding Si cap layer. The interposer is made of high resistivity Si to minimize Rf losses.


They examined different wafer level packaging approaches for fabricating the interposer and populating them using either D2D or D2W bonding of the MMIC components followed by wafer level encapsulation. These are compared in the table below. All of the process flows appear to have issues.

imec 2

Axus Technology

Bob Roberts of Axus presentation “Technology transfer for MEMS and Adv Packaging” was a nicely written review of the use of CMP and the thinning of silicon wafers which I can recommend to those wanting a refresher on the technology.

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 362 Broadcom Continues Consolidation; IMAPS 2017 Part 3

By Dr. Phil Garrou, Contributing Editor

Before we get back to the IMAPS 2017 conference, a few important items:

Consolidation – and the beat goes on

We have talked a lot about consolidation and why it is happening. [see IFTLE 255 “Consolidation continues …” and IFTLE 241 “Simply Obeying the Laws of Economics” ]

On November 6th Broadcom announced its intention to buy its rival, Qualcomm, for ~ $130B, including debt. If successful, it would be the largest deal in the history of the technology acquisitions. Following the consolidation trail, NXP acquired Freescale and Qualcomm is trying to acquire NXP and Broadcom is trying to acquire Qualcomm. Certainly a sequence that no one could have predicted a few years ago. If Broadcom successfully acquires Qualcomm, the combined group would become the world’s third-largest chipmaker, behind Intel and Samsung. If they combine, with no divestments, Qualcomm and Broadcom would control between 50%-60% of the market for Wi-Fi chips and 27% of radio-frequency chips for mobile devices.

The Economist offered the following table listing mega mergers (consummated and in process) [link]

economist 1

The Economist also offers the comment that “with Qualcomm’s pending purchase of NXP and Broadcom’s of Brocade, what looks at first glance like a merger between two giants is actually a four-sided deal. It would be difficult to unite so many different divisions and business units all at once” It certainly will be interesting to see what happens here!

Continuing our look at IMAPS 2017

InFO like FOWLP from ASM Pacific & partners

John Lau representing ASM coauthored the presentation “Fan out Wafer Level Packaging of Large Chips with Multiple Redistribution Layers” with a long list of co-workers. The design is a chips first face up process looking a lot like the TSMC InFO. The detailed descriptions of the processing are much appreciated. The overall process flow is shown below.

asm 1


As is the case for InFO the key processing sequence is plating up the contact pads on the wafer (30um), molding the wafer and hen grinding back the mold cmpd to expose the copper pads much like you would a TSV. Their mold compound is Nagase R4507 a liquid EMC with 85% filler content and an average filler particle size of 8um.

Subsequent processing of the RDL layers is shown below. The smallest L/S features on the bottom RDL layer is 5/5.



From this groups 2nd paper “Characterization of fan-out WLP” we learn that

– die attach accuracy and pitch compensation are the key issues that need to be controlled for accuracy in the RDL process

– die tilt is an important factor that affects the contact pad reveal so the die bonder should be optimized to control leveling

– molding concerns include die shift, warpage and voids. Mold cmpd choice will affect warpage results.

Namics & Hitachi Chemical

The presentation “Development of Liquid Compression Molding (LCM) Materials for Low Warpage” by Namics and Hitachi Chemical detailed the properties required for a low warpage LCM. They were able to substantially reduce LCM warpage by using aliphatic, flexible epoxy resins with low modulus and low cross link density.

Hitachi Chemical

Hitachi Chemical also detailed their studies on “Highly Reliable Cu Wiring Layer for 1/1um L/S using newly Designed Insulation Barrier Film.”

It is generally agreed upon that organic substrates fabricated by the semi additive plating process is limited to 8um L/S . To achieve finer interconnect pitch required by future FOWLP Hitachi Chem has studied trench wiring to create such high density structures. This sequence is typically laser ablation of the trenches in the dielectric, copper plating and subsequent planarization by CMP. Barrier metal is required to minimize copper migration so the seed layer for plating is generally 50nm of Ti followed by 100nm of sputtered Cu. The processes are compared below. For reliable HAST testing of 2/2 L/S they have found that covering exposed Cu with a Ni barrier layer is required.

Hitachi chem 1

They have also examined chemically amplified, negative tone, photosensitive dielectrics to achieve below 2/2 L/S. This processing includes the use of an insulation barrier film which shows low moisture absorption, low anionic impurities and high hydrolysis resistance. Using this combination they were able to achieve 1/1 L/S.

hitachi chem 2

For all the latest in advanced packaging, stay linked to IFTLE…

ITLE 361 2017 IMAPS Part 1: Xilinx HMB Integration Challenges and More

By Dr. Phil Garrou, Contributing Editor

Let’s start looking at some of the key presentations at IMAPS 2017.


Gandhi of Xilinx gave an interesting presentation on “2.5D FPGA-HBM Integration Challenges.”

Heterogeneous integration of HBM (high bandwith memory stacks) with ASIC, GPU, CPU and FPGA is real and progressing quickly. Xilinx is the frst company to attempt HM integration with partitioned FPGAs in a 2.5D format.

Xilinx 1Xilinx recently announced HBM enabled 16nm Ultrascale FPGAs which are shown below. They are built using 3rd gen CoWoS technology jointly developed by Xilinx and TSMC. The claim is that these heterogeneously integrated packages are delivering 10X the bandwidth per HBM stack and 4X lower power than DDR-4 . These packages are 55 x 55mm2.


Interposer Design – µbump pitch on the memory stacks are set by JEDEC standards. There is no std for µbump pitch on FPGAs. For ease of interposer routing, pitches across the two die need to match so that an integer number of inter die signal lines can be routed in a uniform fashion between a pair of micro bumps. This is also required from a signal timing point of view.

Package Design and Process –

xilinx 2HBM-FPGA integration for the current 16nm product required changes to bump structure and lid type. The packages moved from eutectic solder bumps to copper pillar bumps with lead free solder and a change from a copper lid to a stainless steel stiffener ring was also required. This is shown in fig below. Precise control of bare die parallelism and flatness is required to enable heat sink attachment. In the shown figure, modeling shows that co-planarity is reduced by wider ring width and/or thicker stiffener ring. They were also required to change the BGA substrate to a lower CTE core to lower the co-planarity.

Challenges in bump assembly

Addition of the HBM stacks results in open area around the HBM stacks in the layout as seen in the above pic. This results in higher warpage. Bump size and underfill type must be optimized.

ETRI (Electronics and Telecom Research Institute) Korea

ETRI has examined the “Development and Stacking Process for 3D TSV Structures using Laser.”

As part of their 3D studies they have compared bonding results between using TC (thermocompression) and laser. The bonding procedure is shown below.


The max temp of the compression bonding was 240 °C for 200 sec at a force of 1 Newton. At a laser power of 200W the max temp reached was 260 °C at a process time of 10 sec.

They concluded that there was no difference in the solder joint morphology and the electrical resistances of bonded daisy chains for both assembly technologies was the same.


Kobus presented a “Alternative Deposition Solution for Cost Reduction of TSV Integration.” Use of TSV requires isolation, barrier and copper seed deposition into the etched vias. For low AR TSV one uses PECVD and PVD techniques for the depositions. For high AR vias ALD is sometimes required. PECVD offers the highest dep rate but poor conformality. ALD results in near 100% conformality irregardless of AR, but the thickness is limited and he dep time is very slow.

FAST (Fast Atomic Sequential Technology) combines CVD and ALD to reportedly rapidly give thick, conformal depositions.

Oxide liner dep from TEOS is compared below.

Kobus 1

Electrical properties of the deposition are reportedly enhanced with 150 °C deposition resulting in BV or 9MV/cm.

TiN barrier layer is from TDEAT (tetrakisdiethylamidotitanium) and copper seed from Cupraselect™. Copper seed dep comparing FAST with PVD are shown below. They report that the field thickness (on top), resulting from copper deposition to get 200nm of copper at the bottom of a 10:1 AR via, is reduced by 2X which effects the subsequent CMP time to remove it.

kobus 2

Claims of a 24% reduction on TSV processing cost are claimed.

For all the latest on Advanced Packaging, stay linked to IFTLE…