Insights From Leading Edge


IFTLE 377 μ-Transfer Printing going mainstream?; Heterogeneous Int at IMAPS DPC

By Dr. Phil Garrou, Contributing Editor

OSRAM licenses m-transfer printing from X-Celeprint

IFTLE has discussed m-transfer printing for several years, first with Semprius [ see IFTLE 203 “Apple Acquires LuxVue µ-assembly Technology” ] and then at licensee X-Celeprint [see IFTLE 354 “The Case for µLED Displays”]

We have seen Teledyne using the technology in several DARPA programs and have heard rumors of the technology being used to develop mLED displays.

It now appears that a major player in word wide LED component marketplace has significant interest in the technology because OSRAM now reports that they have entered into a technology and patent licensing agreement with X-Celeprint for their m-transfer printing technology (link)

Exactly how will OSRAM use this technology in their LED products?? We’ll be keeping an eye out and report back to our readers…

Xceleprint 1

μ-transfer printing basics [link]

Heterogeneous Integration Roadmap Update at IMAPS DPC

Starting this week we will begin going over some of the presentations at the IMAPS Device Packaging Conf held every year outside Phoenix, AZ. At one of the keynote presentations Raja Swaminathan of Intel discussed his work on the Bill Chen Heterogeneous Integration Roadmap.

If you read this blog regularly you have probably picked up on the fact that IFTLE has little tolerance for bad nomenclature and/or redundant nomenclature. So, let’s consider the term “heterogeneous Integration” what this means is basically combining (i.e integrating) things that are not the same (i.e. heterogeneous)…i.e. a DRAM memory module is not heterogeneous integration (but would be homogeneous integration) . So is this something new ?? In the 1990s we called them multichip modules. Today that is also called a SiP. Too many terms meaning nearly the same thing for my liking.

But…given that the community has appeared to latch onto this catch phrase lets look at what the roadmap committee is doing about the naming.

Swaminathan makes the point that on package integration is more compact, low power and higher band width than off package connections (see below).

Intel 1-2

In order to improve on the meaningless terms 2.5D, 2.1D etc they are proposing that we consider these as 2D enhanced architectures as side by side active silicon interconnected at high densities using either organic or silicon based interposers.

intel 2-2

So, TSMC’s CoWoS would be 2DS with TSV, ASEs FoCoS would be 2DO chips last and Intel’s EMIB would be 2DS without TSV.

Intel 3

Technologies are compared I terms of density below:

Intel 4

Swaminathan concludes with a slide showing on of the main themes of IFTLE for the past decade “Packaging technologies will become more wafer-fab like.”

Intel 5

 

For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 376 ASE / TDK launch ASE Embedded; The AI Ecosystem Develops

By Dr. Phil Garrou, Contributing Editor

ASE, TDK Embedded Chip Joint Venture begins

Taiwan’s ASE has initiated a joint venture with Japan’s TDK Corp to produce embedded packaging solutions in Kaohsiung Taiwan. ASE has 51% ownership in the venture which currently employs 150 people.

With initial capital of $51MM , ASE Embedded Electronics Inc has started operations manufacturing embedded substrates using TDK’s (SESUB) technology (see IFTLE 238 “ASE & the Apple watch, ASE / TDK JV…” and IFTLE 347: “ASE Embedded Packaging Solutions” )

ASE 1-4

AI vs IoT

AI and IoT both buzz words that are predicted to drive the electronics industry over the next decade. ITLE is bullish on AI, not so much on IoT. As I have explained before my opinion is formed from a packaging perspective and while I think AI will need all the latest high end packaging solutions, I still perceive that most IoT will require the absolute lowest cost, stripped down packaging available. AI platforms are an intimate combination of hardware and software but certainly will be requiring the latest that we have to offer in high end packaging solutions.

AI processing will go into home control devices, autos, surveillance systems, airplanes, wearables and things we have yet to think of. AI processing is unique in that traditional customers Amazon, Google and Apple, have begun to design their own AI chips, in hopes of differentiating their products from those of rivals. This has major ramifications for companies like Intel and Nvidia, which will now be competing with their customers.

While I certainly am not an AI expert, we all must quickly up our knowledge in this area which I see leading advanced packaging into the next decade. A list of current participants has recently been compiled (shown in the table below) (link)

table

Recently on “Graphics Speaks” Kathleen Maher has looked at how some of these cloud companies, IP companies, and the traditional semiconductor companies all have conflicting ambitions in the AI market place . I recommend reading the full article.[link]

While cloud companies like Google appear to be favoring custom chips to augment CPUs and GPUs, Semiconductor and IP companies are designing chips to enable efficient hardware and neural net systems and Intel is proposing an open platform ecosystem based on Xeon, FPGAs, and specialized processors like Nervana and Saffron.

Google

Google’s Tensor Processing Unit (TPU), was introduced last year. Their initial beta customer Lyft, is using AI to recognize surroundings, locations, street signs etc. The cloud-based TPU features 180 teraflops of floating-point performance through four ASICS with 64 GB of high bandwidth memory. These modules can be used alone or connected together via a dedicated network to form multi-petaflop ML supercomputers that they call TPU pods.

Apple

The best known mobile AI processor is included in the Apple iPhone X. Apple’s A11 is a 64-bit ARM 6 core CPU with two high performance 2.39 GHz cores called Monsoon, and four energy efficient cores, call Mistral. The A11’s performance controller gives the chip access to all six cores simultaneously. The A11 has three-core GPU by Apple, the M11 motion coprocessor, an image processor supporting computational photography, and the new Neural Engine that comes into play for Face ID and other machine learning tasks.

Amazon

Amazon is reportedly developing a chip designed for artificial intelligence to work with the Echo and other hardware powered by Amazon’s Alexa virtual assistant (link). The chip should allow Alexa-powered devices to respond more quickly to commands, by allowing more data processing to be handled on the device vs the cloud.

Nvidia

Nvidia has announced its new Volta GPU with 640 tensor cores, which delivers over 100 Teraflops. It has been adopted by leading cloud suppliers including Amazon, Microsoft, Google, Oracle , and others. On the OEM side, Dell EMC, HP, Huawei, IBM and Lenovo have all announced Volta-based offerings for their customers.

Microsoft and Intel’s “Brainwave”

Microsoft has teamed with Intel and is offering their Stratix 10 FPGAS for AI processing on Microsoft Azure (see below) codename “Brainwave” (link) . Intel is proposing FPGAs  + processors for AI work. Intel is reportedly focusing on the Stratix X FPGA as a AI companion to Intel’s Xeon processors.

Microsoft

 

Intel’s 14 nm Stratix 10 FPGAs accelerate Microsoft’s Azure deep learning platform using FPGAs with “soft” Deep Neural Network (DNN) units synthesized onto the FPGAs instead of hardwired Processing Units (DPUs). Brainwave is designed for live data streams including video, sensor feeds, and search queries.

Intel

Intel is making a major play in AI. Intel has multiple processor options for AI, including Xeon, FPGAs, Nervana, Movidius, and Saffron (link).

Saffron Technology was acquired by Intel in 2015. It develops “..cognitive computing systems that use incremental learning to understand and unify by entity (person, place or thing) the connections between an entity and other “things” in data, along with the context of their connections and their raw frequency counts…. Saffron learns from all sources of data including structured and unstructured data to support knowledge-based decision making.” It is being used extensively in the financial services industry.

In 2016, Inte­­­l announced acquired Nervana, a startup developing AI software and hardware for machine learning. In 2017, Intel revealed the Nervana Neural Network Processor (NNP) designed expressly for AI and deep learning.

Intel acquired Movidius in 2016 to get VPU (visual processor unit) technology for machine learning and AI. Intel’s Movidius devices include dedicated imaging, computer vision processing, and an integrated neural compute engine. Applications for VPUs include automobile license readers at bridges and toll roads, airport security screening, drone surveillance and the many applications of facial recognition.

ARM – Trillium Platform

The Arm Trillium Platform includes Machine Learning (ML) and Object Detection (OD) processors with Arm software, and the existing Arm compute library and CMSIS-NN Neural Network kernels.

 

It will be interesting to see hope the packaging community develops solutions that will be compatible with these advanced high speed HPC applications.

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 375 EVG / IBM Laser Debonding; Samsung Increases Focus on CMOS Image Sensor Mkt

By Dr. Phil Garrou, Contributing Editor

EVG Licenses IBM Laser deBonding Tech

IBM’s Hybrid Laser Release Process has been licensed by EV Group for inclusion in their low-temperature laser debonding equipment (link).

The IBM technology will reportedly help EVG address the industry’s requirements for temporary bonding and debonding, including high throughput, low wafer stress for high yield, and low cost of ownership of the laser equipment, processing and consumables. The EVG offering will encompasses techniques to help protect chips from heat and laser damage, as well as chemical clean technologies for device and carrier wafers.

The IBM technology was first described at the 2010 IEEE ECTC Conf (link)

Post debond cleaning is a topic that is rarely discussed but very significant from a manufacturing standpoint. Following debonding, residual polymer materials are left on the substrate. The residue level is dependent on the ablation condition. Laser fluence and total accumulated number of laser pulses need to be optimized for a given polymer adhesive. After debonding, any residue or remaining polymer adhesive needs to be cleaned prior further processing. The cleaning may be accomplished by several approaches including dry etching or chemical wet etching.

EVG 2

 

Designed for integration in the company’s benchmark EVG-850DB automated debonding system, EVG’s laser debonding modules incorporate a solid-state laser and optics designed to enable force-free debonding. Featuring both low-temperature debonding and high-temperature-processing stability, EVG’s laser debonding solution is available for a variety of applications including FO-WLP (below), memory stacking, die-partitioning, heterogeneous integration etc.

EVG debonding

Samsung to Challenge Sony on CMOS Image Sensors

Fresh from their overtaking of Intel as the worlds #1 IC Chip producer, ETNews (Korea) reports that Samsung has reportedly now set its sights on Sony and CMOS Image sensors. (link)

Samsung Electronics is reportedly planning to increase its production capacity of image sensors and it has set a goal to become #1 in the image sensor market.

Since 2017, Samsung has reportedly been working to convert its line 11 in Hwasung that was used to produce DRAMs into a line (S4 line) that would be used to produce CMOS image sensors (CIS). Conversion to the S4 line is expected to be completed by end of this year. According to ETNews Korea , when this process is done, Samsung Electronics is going to immediately start the conversion process of its 300mm line 13 in Hwasung, that is used to produce DRAMs, into another line that will be used to produce image sensors. Line 13 line can produce about 100,000 units of DRAMs per month, but because image sensors ae a more complex deposition process, it is expected that production capacity for CIS will be reduced by about 50% after conversion. They further report that Samsung Electronics will have a total production capacity of 120,000 units / mo of CIS after these conversion processes are over.

SONY and Samsung are both commercializing 3D stacked image sensors (sensor + logic + DRAM) that can process 960 frames per second (slo-mo). Samsung Electronics has launched the new ISOCELL Fast 2L3 image sensor for super slow-motion recording (link).

The Samsung ISOCELL Fast 2L3 is a high speed 3 layer 3D stacked CMOS image sensor designed with a 2 Gb LPDDR4 DRAM attached below the analog logic layer. With the integration, the image sensor can temporarily store a larger number of frames taken in high speed quickly onto the sensor’s DRAM layer before sending frames out to the mobile processor and then to the device’s DRAM. This allows the sensor to capture a full-frame snapshot at 1/120 of a second and also to record super-slow motion video at up to 960 frames per second ( 32 times the typical filming speed of 30 fps).

samsung

The design is similar to that of Sony who was the first to report integration of DRAM into the 3D CIS stack (see IFTLE 272 “2015 3D ASIP Part 1: Pioneer Awards; Sony 3D stacked CIS; Latest on SPIL Acquisition”)

ETNews reports that the number of customers purchasing Samsung image sensors is currently over 10 as Samsung Electronics is increasing points interactions with major mobile devices and automotive customers.

For all the latest on advanced packaging, stay linked to IFTLE…

 

IFTLE 374 IMAPS Device Pkging Conf part 1: 3DIncites Award Winners

By Dr. Phil Garrou, Contributing Editor

The 14th Int Conf on Device Pkging was held at its normal site, Ft. McDowell, AZ, last week. I normally show a picture of the general chair of the meeting and I will this time also (below), but I thought it was about time we gave due credit to the IMAPS staff that makes the meeting possible.   Below we see (L to R) Dir of Program Dev, Brian Schieman; Membership Admin, Shelby Moirano and Exec Dir Michael O’Donoghue. Events Mgr Brianne Lamm was back in NC holding down the fort, so to speak.

IMAPS CREW

 

On Tuesday night, we were all entertained by a local Indian tribe that showed us their various ceremonial dances. Below Chairman Ramm poses with the tribes dancers.

Ramm & the Indians

 

The most entertaining event of the conference was certainly the 3DInsights awards gala on Wednesday night which included, in addition to the awards ceremony, a barbecue dinner, an awards ceremony quiz and a dress up photo booth.

There were 40 nominees from 26 companies and four research institutes competing for awards in 9 categories. An amazing 40,619 votes were cast online. Winners were:

Device Manufacturer of the Year: Amkor Technology for its acquisition of NANIUM.

Device of the Year: (tie) M-Series ™ Deca Technologies, and OmniVision Technologies. Deca was nominated for their adaptive processing technology combined with planar front side molding. OmniVision was nominated for their Nyxel technology which allows their image sensor to see better and farther under low- and no-light conditions than previous generations.

EDA Supplier of the Year: Mentor, A Siemens Business was nominated in recognition of the efforts of Juan Rey, VP of Engineering, at a number of 3D-IC focused conferences in 2017.

Engineer of the Year: Gill Fountain, Xperi (Ziptronix) was nominated for expanding the chemical mechanical polishing process window for Cu damascene image sensor processing.

Equipment Supplier of the Year: FRT GmbH was nominated in recognition of its third gen surface metrology tools that combine multi-sensor technology and hybrid metrology in one measuring system.

Material Supplier of the Year: Semblant for their MobileShield technology, a nano-coating that protects mobile phones from water damage and corrosion.

Process of the Year: F.A.S.T., KOBUS  was nominated for combining the CVD and ALD deposition.

Research Institute of the Year: Fraunhoffer IZM  was nominated for launching a consortium to bring research and industry together on all questions of implementing panel level packaging (PLP)

The dress up photo booth was certainly lots of fun. Below we see General Chair Peter Ramm, 3DIncites Francoise von Trapp and a group shot of the nights award winners.

awards

Proceeds from the event went to two charities: the IMAPS Microelectronics Foundation, which exists to support student activities related to the study of microelectronic packaging, interconnect and assembly; and Phoenix Children’s Hospital pediatric oncology programs which exists to save children with cancer.

Next week we will start to look at some of the key presentations.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 373 Semi ISS Part 2: ASE’s Hunt describes “Transformative Fan-Out” Packaging

By Dr. Phil Garrou, Contributing Editor

Finishing up our look at the 2018 SMI ISS meeting, let’s take a look what John Hunt, ASE, had to say about the “Transformative Power of Fan-Out.”

Without question so called “fan-out packaging” has become the new packaging buzz word having replaced 3D-IC a few years ago. Focus on this technology has quickly (vs 3DIC) produced significant technical advances and led to broad commercialization. Although IFTLE has covered this technology in detail since its inception by Infineon, it is always good to review it one more time, which is what John Hunt did for the mostly front end folks assembled at Half Moon Bay.

Hunt’s slide shown below is an extension of the well worn slide showing why wafer level packaging developed with a low cost structure, i.e. the packaging was done on the wafer before dicing. Hunt contends, correctly, that the same is true for the WL FO WLP, though I would add that this also shows why the early eWLB structures from Infineon couldn’t get down low enough in cost for major market penetrations, i.e. the extra steps involved with creating the reconstituted wafer.

ASE 1-3

Fan Out Enables Multi Die Packages

  • Advanced technology nodes increase wafer cost
  • Fan out allows partitioning into different nodes
  • Fan out allows partitioning of functionality
    • Digital, Analog, Components, MEMS, and IPDs

ASE 2-2

Fan out can be done either chips first or chips last as shown below. The newer chips first, face up (followed by planarization) and chips last options have resulted in much higher density interconnect which has allowed competition with some of the silicon 2.5D applications.

The high density fan out chip on substrate (FOCoS) is capable of 2/2.5um L/S and 4 metal layers as shown below:

ASE 4-2

 

Significantly thinner PoP can now be fabricated I much thinner formats:

ASE 5

In addition, they are still looking at moving FOWLP technology to large panel format in an attempt to continue to lower costs even further.

For all the latest in Advanced packaging, stay linked to IFTLE…

IFTLE 371 Semi ISS: Market Opportunities and Drivers

By Dr. Phil Garrou, Contributing Editor

Let’s take a look at some of the presentations given at the Semi ISS (Industry Strategy Symp) conference in January at Half Moon Bay.

VLSI Research

Lati of VLSI Research discussed “Market Opportunities in the Coming Technology Disruptions”

Six companies are now responsible for > 70% of Capex spending. Memory Capex hit $45B in 2017, more than 50% of total spending.

Fig 1 VLSI Res

– Samsung accounted for more than half of DRAM spending in 2017. Other suppliers will have to respond with increased spending in 2018 to prevent share losses.

Semiconductor assembly equipment is expected to account for $5.2B in sales in 2018 with assembly equipment trends shown below.

FIG 2 VLSI Res

 

Versum Materials

Novo of Versum Materials discussed “The Semiconductor Industry from a Materials Suppliers Perspective.” He listed the following forces acting on Materials suppliers:

Fig 3 Versum

Consolidation means fewer and much larger customers…

  • Customer Centric vs. Market Centric model
  • Higher pressure
  • Access is critical for more limited POR opportunities
  • Risk/Rewards are greater
  • Too many suppliers for shrinking customer base

Shift to Asia requires footprint changes in terms of:

  • Supply
  • Distribution
  • Innovation

Giga sized fabs mean:

  • Greater Customer Expectations
  • Implications of Winning/Losing
  • Increased Ramp Complexity, Volume & Variability

They list the following as Criteria for Success in the 2020s:

Fig 4 Versum

IHS Markit

Jelenick of HIS Markit discussed Global Semiconductor Market Trends. Their breakout of the consumer electronics market by IC categories follows:

Fig 5 IHS 1

Electrification, automated driving and connectivity are expected to drive the growth in the automotive sector.

fig 6 IHS 2

 

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 371 RIP 3D-ASIP: 2004 – 2017

By Dr. Phil Garrou, Contributing Editor

The 14th 3D ASIP Conference (3-D Architectures for Semiconductor Integration and Packaging) has officially ended. It was decided that the longest running focused 3DIC conference was no longer needed by the community since the technology is now fully commercialized in 3D memory stacks and numerous high end applications. For sure, there will be further advances in 3D, 2.5D and ancillary technologies, but it was felt that they could best be handled at your standard advanced packaging conferences. As they say “It’s best to go out when your still on top.”

3-D Architectures for Semiconductor Integration and Packaging, or 3D ASIP as it became known, started in 2004 sponsored by RTI International as a means of showcasing its wafer to wafer bonding technology being developed by spin out Ziptronix. Through the first 12 years it was organized under RTI’s Matt MeCray, who, although not a technologist in the area, developed the vision of having a conference on 2.5/3D technology focused on commercialization and business issues and focused on corporate and Institute “invitation only” presentations. For 14 years, hundreds of 3D practitioners assembled in Burlingame CA ( except for a 1 years hiatus in AZ) in early December to discuss the latest breakthroughs in the area. I joined the team as a program chair in 2008 working with Matt to define the programs content /speakers. After working with Matt for 7 years he moved on to do other things in RTI after the 2014 meeting. In 2016 RTI transferred the meeting to IMAPS where it has resided the past two years being chaired by Mark Scannell – Leti, Mitsu Koyanagi-Tohoku Univ. and myself. Below you will find some photos of those involved with the conference through the years and those who have served as program chairs.

A personal thank you to all presenters, who were a who’s who of the 2.5/3D world, and attendees. For me it was an enjoyable decade. I hope it was informative and enjoyable for all of you as well.

3DASIP pics chairs

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 370 3D-ASIP Part 3: Bonding and Assembly in HBM Memory Stacks

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 14th annual 3DASIP Conference.

K&S

Tom Strothmann of K&S discussed the requirements for HBM Memory Stacking. High Bandwidth Memory (HBM 1,2) are currently assembled using C2W compression bonding. Production is mostly done by memory suppliers as opposed to OSATS. HBM 3 is projected for 2019.

K&S 1

There are two prominent stacked die process flows:

    • TC-CUF (Thermocompression with Capillary Underfill)
      • Die by die stacked using TCB
      • Die stack tacked followed by mass reflow
    • TC-NCF (Thermocompression with Non-Conductive Film)
      • Stacked die by die using TCB
      • Die stack tacked followed by Collective Bond
      • Die stack tacked followed by Gang Bond

Cost reduction has focused on units/hr for the TCB process:

    • Bondhead temperature ramp speed
    • Target and die material handling systems
    • Number of bondheads and accuracy requirements

Tacking has the potential to move machine UPH from 1700 to 3500 for a 4 die stacked process using NCF if a separate gang process is used.

K&S 3

 

TSV Die Stress and Warpage

  • Silicon thinned to 50 microns during the via reveal process then has backside dielectrics and UBM applied
  • Imbalanced stress resulting from the dielectrics, metals and pillars on the front of the wafer as compared to the back of the wafer causes warpage in the thinned silicon wafer
  • Stress remains after dicing, resulting in die bowing that can be as much as 40um in a 9x9mm die

TCB with CUF Process

  • TC-CUF processes have been used for stacked die production in HVM. Flux dip before placement followed by capillary underfill is a mature process.
  • Typically lower throughput because the flux dip must be done below 100ºC to avoid premature activation of the flux. UPH >1000 is still possible during bonding with a dual head machine.
  • TC-CUF die stacks have a narrow process window due to thin die warpage. Single die can be held flat during the bonding process , the next die in the stack does not. Heat is conducted through the thin silicon and Cu pillars into the die below, causng solder remelt and relaxation to original warped shape resulting in BLT variation. Since the top die is still held flat, this can create inconsistent bondline thickness throughout the stack.

TCB with NCF (non conductive film)

  • NCF has the benefit of locking the BLT during the bonding process to enable a “flat die” process and more consistent bond lines
  • TCB process can be optimized independent of die stack position
  • Potential to remelt a lower die and change BLT is removed, enabling better process capability
  • But…high forces may be required for bonding some layers based on die size and pillar count

As shown below the thickness of the NCF must be exact or the interface will suffer from particle entrapment or voiding.

K&S 2

Strothmann also offered the following opinions on alternative bonding approaches:

  • Cu-Cu bonding is an area of active development work but is less likely to be applied to memory stacking in the near future
  • Direct (hybrid) bonding of chip to wafer is unlikely for memory stacking

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 369 Samsung HBM2; Ultra Fine Pitch Interconnect; Thin Die Pick and Place

By Dr. Phil Garrou, Contributing Editor

First introduced in June 2016, the Samsung HBM2 consists of eight 8Gb HBM2 dies and a buffer die at the bottom of the stack, vertically interconnected by TSVs and µbumps. With each die containing over 5,000 TSVs, a single Samsung 8GB HBM2 package has over 40,000 TSVs. Including spares TSVs ensures high performance, by enabling data paths to be switched to different TSVs when a delay in data transmission occurs. The HBM2 is also designed to prevent overheating beyond certain temperature to guarantee high reliability. The HBM2 reports a 256GB/s data transmission bandwidth, offering more than an 8X increase over a 32GB/s GDDR5 DRAM chip. With capacity double that of 4GB HBM2, the 8GB solution contributes greatly to improving system performance and energy efficiency, offering ideal upgrades to data-intensive, high-end computing (HPC) applications that deal with machine learning and graphics processing .

Last week Samsung announced that it has started mass production of its 2nd-generation 8-gigabyte (GB) High Bandwidth Memory-2 (HBM2) with the fastest data transmission speed on the market today.[link] Dubbed “Aquabolt”, it is claimed to be the industry’s first HBM2 to deliver a 2.4 gigabits-per-second (Gbps) data transfer speed per pin, at 1.2V for the supercomputing and the graphics card market.

This performance is reportedly 50% greater than the 1st-generation 8GB HBM2 package with its 1.6Gbps pin speed at 1.2V and 2.0Gbps at 1.35V.

A single Samsung 8GB HBM2 package will offer a 307 GBps data bandwidth, achieving 9.6 times faster data transmission than an 8 gigabit (Gb) GDDR5 chip, which provides a 32GBps data bandwidth. Using four of the new HBM2 packages in a system will enable a 1.2 terabytes-per-second (TBps) bandwidth.

In addition, Samsung increased the number of thermal bumps between the HBM2 dies, enabling better thermal control in each package. The new HBM2 also includes an additional protective layer at the bottom, which increases the package’s overall physical strength.

Samsung HBM2

 

Continuing our look at the presentations at the 14 3D ASIP Conference.

Micross – Ultra Fine Pitch Interconnect

Matt Lueck of Micross gave a presentation on their Ultra fine pith interconnect technologies that are being used in their Northrup Grumman (NGC) DARPA CHIPS program discussed in IFTLE 367 [link].

Fine pitch (< 80 um), Cu pillar thermo-compression bonding (TCB) has been widely adopted for advanced packaging of stacked memory and many other applications. Major foundries and assembly houses are offering Cu pillar down to 30 – 50µm pitch with 20 – 30µm pitch in development. Availability of fine pitch Cu pillar bumping from foundries and OSATs are limited to high volume customers and off-shore processing.

Micross has been developing fine pitch technologies over the years under their previous ownership ( Microelectronic Consortium of NC (MCNC) and Research Triangle Institute (RTI). They re positioning themselves as a source for prototype and small volume production of such ultra high pitch interconnect.

They have used 10µm pitch Cu/Sn – Cu bonding in multiple programs since 2007 such as large area array detector applications. They report that such interconnect have shown proven reliability, even for heterogeneous integration with CTE mismatch issues.

  • For next generation area array imaging applications, sub-10 µm pitch electrical interconnects are desired between detector chip and ROIC
  • A process for the fabrication and bonding of 5 µm pitch Cu-Cu interconnects was demonstrated
  • I-V curves indicate ohmic behavior of interconnect chains
  • Leakage current measurements indicate > 100 GΩ isolation between adjacent channels of interconnects
  • Demonstrated high yield on 1280 x 1024 array sample

Micross 1

Working with NGC they are developing 4 – 10µm pitch gold-gold bonding technology. The evaporated gold bumps show RMS roughness of 3.7-3.9nm.

micross 2

BESI- Thin Die Pick and Place

Stefan Behler of Besi discussed “How to peel Ultra this dies from Wafer tape”

Behler describes 4 key properties as shown below:

BESI 1

(1) Wafer foil peel force depends on the foil type and the peel speed as shown in table below.

besi 2

(2) edge peel force depends on the dicing method

(3) Bending stress depends on the Ejector type with thinned die resulting in more bending stress.

besi 3

 

(4) die strength appears (measured by 3 point bending test) is almost independent of thickness but is dependent on :

  • surface (active structure)
  • backside (grinding, polishing…)
  • edges (dicing)

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 368 IMAPS addresses the Chip-Package Interaction (CPI)

By Dr. Phil Garrou, Contributing Editor

This week, I am interrupting our look at the 2017 3D-ASIP conference to take a look at consolidation in the equipment industry and the recent issue of IMAPS Advancing Microelectronics magazine.

Equipment Consolidation

IFTLE has explained many times that a sure sign of industry segment maturity is when the 3 top players have a combined > 80% market share. The best examples of this currently are hard disk drives and DRAM memory.

The latest data on the equipment industry market shares points to this segment being very close [link] . Had the TEL/ AMAT merger gone through, the industry truly would have reached the definition of maturity. I would be looking for attempts at other combinations in this segment to be coming soon.

equipment

Chip Package Interaction

Urmi Ray, VP of Technology for STATS ChipPAC (JCET) has edited a special edition on the chip-package interaction, which is definitely worth a read [Advancing Microelectronics, Nov/Dec 2017, V44, No 6.][Link]

As most of you know, CPI is the interaction between the semiconductor package stresses and the semiconductor device. Package stresses are caused by thermal, mechanical and chemical mechanisms. CPI contributes to various failure modes during package assembly and field life. The emergence of both fan in and fan out wafer level packaging, while delivering unparalleled form factor and cost improvements by eliminating the package substrate, has resulted in loss of a buffer layer between the chip and PCB resulting in additional stresses being transmitted to the die surface during SMT assembly.

Qualcomm

Zhao and co-workers at Qualcomm discussed the “Electrical Chip- Board Interaction (e-CBI) of Wafer Level Packaging Technology”.

The industry is clearly moving packaging technology toward WLP and Fan-Out WLP to reduce packaging cost and form factor. One of the key dif­ferences between Flip Chip CSP (FCCSP) and WLP/FOWLP is the absence of a package substrate in the latter packaging options. For e-CPI in FCCSP, the package substrate isolates the chip from the PCB. Without the package substrate, the silicon die in WLP/FOWLP directly inter­acts with the PCB board. The mediation of the board stresses by the packaging substrate is now gone and one must evaluate the risk of direct PCB stress on the chip, i.e. electrical chip-board interaction (e-CBI). For WLP and FOWLP, e-CBI can be signifi­cant.

For example, they point to the fact that visual in­spection of FOWLP reveals dimple patterns on the backside of the parts after board level underfill which correlate with the pat­terns of BGA depopulation. In the absence of the mechanical support from BGA solder balls in the depopulated areas, the board level underfill shrinkage pulls the thin silicon die to­wards PCB. FEA models have verified this phe­nomenon and reproduced similar “dimples”. Since the silicon die bends toward PCB in the BGA depopulated regions, this infers that tensile stress is being created on active silicon surface.

qualcomm 1

 

AMD

Ivor Barber and co-workers discussed “14nm Chip Package Interaction Technology Development.”

With the implementation of extreme low K (ELK) porous dielectric materials (k < 2.5) into the back end of line (BEOL) to reduce the in­terconnect capacitance and cross-talk noise and enhance circuit performance, the lower mechanical strength of the ELK, along with increased die size, difference in effective coefficient of thermal expansion (CTE) between die and substrate, and the use of higher stiffness lead free solder increasingly contribute towards ELK layer cracking. Chip package interaction (CPI) be­came one of the critical reliability issues that needed to be addressed to avoid electrical or mechanical failure in products.

In order to evaluate CPI risk and reliability concerns from a technology point of view, they developed a CPI test vehicle (TV) which must include the same BEOL stacks, same ELK ma­terial, same BEOL process, same bump technology, same substrate technology, same assembly process for the pro­duction of the same Si node. In their 14nm CPI development, a 14nm TV with die size of 21×21 mm2 with 140um bump pitch of SnAg bump has been selected. 40×40 mm2 substrate has been used in our CPI technolo­gy qualification. JEDEC standard tests (Precon, UBHAST, TCJ, MSL, and HTS) were used as criteria for the CPI tech­nology qualification.

ELK delamination / cracks called “white bumps” are encountered as rigid lead free bumps would transfer more stress to weak ELK layers causing ELK crack underneath the bump. Unlike bare silicon dies, thermal deformation of pack­aged dies can be directly coupled to Cu/low-k or ELK interconnects, inducing very high local stresses to drive fracture and delamination. ILD delamination is caused due to dicing defects like micro-cracks and poor adhesion or mechanical strength of low-k/ELK dielectric materials under the thermal load of the processes like flip-chip as­sembly process or thermal cycling tests.

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In order to improve the CPI margin, studies have examined passivation thickness, polyimide thickness, under bump metallization, CTE of substrate, and FBEOL. Simulation and DOE have shown that by using thicker Aluminum terminal metal and two layers of passivation, the CPI risk reduced significantly. So foundries have now implemented this dual pas­sivation layer with Al terminal metal to enhance CPI reli­ability.

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Simulation has shown that ELK stress are reduced with reduced bump pitch.

The fracture toughness of low-k/ELK dielectrics vs SiO2, is substantially reduced and is significantly lower than that of Si. It is thus much easier to induce defects like micro-cracks during dicing. Those tiny cracks can develop and propagate into the active die area and cause failure un­der thermal-mechanical stress. One approach to prevent cracking at the die edge or die corner is to apply patterned metal structures called crack stop around the perimeter, especially reinforced at the die corners. They found that double wall crack stop was necessary for products with large die size to provide protection for the dicing defects.

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