By Dick James, Chipworks
Earlier last week, a couple of laptops arrived from Japan using the Core M version of Intel’s Broadwell processor. Straight into the lab, and within a few hours the first sight of the die structure, confirming that it is indeed the 14nm technology.
The first image below is an image of a die that was given a bevel polish, so that we can look at the transistors in plan view. It’s a bit fuzzy, due to the high magnification, and construction we have going on next door; but we have measured ten contacted gate pitches as you can see, and that looks pretty close to the 70nm that was announced by Intel back in August.
On another part of the bevel we can see the fins, and here we have counted 20 pitches (third image above). Which agrees with the 42nm pitch in the Intel webcast. So far, so good!
If we look at the cross-section (fourth image), Intel has stayed with their thick top metal that they have been using since the 65-nm node, which means that we have to squint awfully hard to see THIRTEEN layers of metal, and a MIM-cap layer under the top metal.
A look at the edge seal (fifth image), which doesn’t have the top metal or the MIM-cap, makes it easier to count twelve layers. We are used to seeing twelve-plus metal layers in IBM chips (their 22nm Power8 has fifteen!), but Intel has been using nine for the last few generations, going up to eleven in the Baytrail SoC chip.
Intel quoted 52 nm interconnect pitch, but we see 54nm (sixth image). Although that is within measurement error, and we may not have sectioned the most tightly packed part of the die.
As yet we don’t have any detailed TEM imaging to look at the transistors or fins in close-up, so we can’t verify if the fins have vertical walls or not, as shown by Intel (seventh image).
The cross-section seems to show that essentially the 14nm process is a shrink of the 22nm technology, with the modified fins; the gate metallisation looks similar to the 22nm, with tungsten gate fill as in the earlier process. (As an aside, this will make it the fourth generation replacement metal gate process – this technology has legs!)
Intel and IBM are giving late news papers at IEDM in December, and apparently there are air gaps in the back-end dielectric stack – we have not found those yet. We have confirmed the SRAM cell size in the cache memory is ~0.058 µm2.
Our analysis is ongoing, and we look forward to some great images!
Aren’t V1, V2 and V3 embedded (gouged) into their lower level Cu lines? It looked to me like that. If Intel did form recesses in the lower level Cu lines without protecting the exposed via openings, dielectric layers in which the via openings were formed would have been contaminated with Cu very much. This is thought to have caused leakage and low TDDB of interconnects. Thanks for your opinion in advance.
Looks like there is a short and the DB is not CMP clean.
This will get escalated.