The Next Transistor


We are in the age of the FinFET, which may soon feature III-V channels. Longer term, CNTs and graphene may come into play.

Technologies such as strained silicon, high-k metal gates and FinFETs have enabled smaller transistors, which improve packing density and lower the cost per transistor. Moving forward, the goal is to continue to increase density and reduce cost, but also to improve energy efficiency by limiting leakage and lowering the power supply.

FinFETs, which were rolled into volume production by Intel last year, will likely be the transistor of choice for many years to come, as others follow Intel's lead. Transistors with high-mobility channel materials, such as InGaAs, offer tremendous promise, particularly when implemented in a quantum-well FET (QWFET) design (but they can also be implemented in a FinFET).

Eventually, a move to the next "switch" will be required. It might be transistor ??? a spin-transistor or a tunneling transistor, for example ??? but it could be some other kind of switch, perhaps based on carbon nanotubes (CNTs) or graphene. Early work shows good results, but it's a long road from the lab to volume production, often many decades.

As Intel's Mark Bohr noted in his keynote address at the 2011 International Electron Devices Meeting (IEDM) in December, traditional MOSFET scaling has served the industry well for more than three decades by providing continuous improvements in transistor performance, power and cost. However, with the growing market interest in mobile products with long battery life, and growing need to lower the energy cost of running large data centers, there is more interest in reducing transistor leakage current and operating voltage [1].

Intel's announcement in May of last year was historic in the world of transistor evolution. The announcement was that the 3-D transistor design called tri-gate, first disclosed by the company in 2002, would be moved into high-volume manufacturing at the 22nm node in an Intel chip codenamed "Ivy Bridge." In the second quarter of this year, Ivy Bridge will ramp to nearly 25% of Intel's processor production.

Figure 1. Intel's 3-D Tri-Gate transistor structure provides improvements in performance, leakage power and active power.

Offering improvements in performance, leakage power and active power, tri-gate transistors ??? also called FinFETs because of their "fins" as shown in Fig. 1 and Fig. 2 ??? are in the general category of multi-gate transistors that have fully depleted operation. Fully depleted devices can offer three forms of improved transistor operation: lower off-state leakage, higher performance and/or lower active power [1]. The tri-gate structure wraps the gate electrode around three sides of tall and narrow silicon fin, providing improved electrostatic control of the channel region compared to a traditional planar device. The improved channel control results in a steeper sub-threshold slope which can provide up to a 10X off-state leakage reduction. The improved channel control also enables gate length scaling, which benefits both area scaling and reduces gate capacitance.

Figure 2. This image shows the vertical fins of Intel's tri-gate transistors passing through the gates.

Alternately, the tri-gate device can be operated at a lower threshold voltage with the same leakage as a planar device. This lower VT can be used to provide either higher performance or allow lower operating voltage for reduced active power. 22nm tri-gate transistors provide a 37% gate delay improvement at 0.7V or a 50% active power reduction at constant performance when compared to Intel's 32 nm logic technology on a comprehensive set of benchmark circuits.

Long live the FinFET!

With the advantage of FinFETs firmly established, the rest of the industry is following suit. "Today, what the foundries are focused on, GLOBALFOUNDRIES in particular, is the FinFET," said David Bennett, vice president of alliances for GLOBALFOUNDRIES, speaking at SEMI's Advanced Semiconductor Manufacturing Forum (ASMC) in May. "The initial introduction will be around 20nm-type design rules. Once we get 'on the fins,' there's going to be an absolute, strong motivation across the entire IP ecosystem to maintain that architecture and to continue to drive price/performance and cost down. We'll do that through improved dimensional controls on heights and profiles of the fins, as well as materials, such as III-V channels. We'll also really work on Vdd scaling."

Subu Iyer, IBM Fellow and Chief Technologist at the Microelectronics Division, IBM Systems & Technology Group, also spoke at ASMC. "I dare say that everybody in the next generation, 14/15nm or whatever nanometer technology we're talking about, is going to be using FinFETs," he said. But he also noted that, for the first time in the industry's history, the cost per transistor has not decreased with a new technology generation. "If you look carefully, it does not buy us the density that we're used to. It's not the 0.7 scaling that doubles the number of circuits per unit area," he said. "It's also not really buying us power. If we were following Danard's scaling, which he proposed back in the late '70s, we should have been sitting around 300 or so mV of Vdd supply. We're not. Why? Because, from a circuit perspective, we don't have noise immunity at those low voltages. That's a problem," he said.

All of these factors have many calling for a new way of thinking. "The next step of innovation, and the next step for our R&D dollars, has to be in figuring out what are we going do to actually reduce power dramatically. If you look at where we are today, the power/circuit ??? even though it's very impressive for all of our handheld appliances and so on ??? is still way, way out of the league of biologically competing systems, for example," Iyer said. "I believe quite honestly that there is something that is going to come from some other direction that is really going to upset this whole apple cart." He noted that the supercomputer Watson may have won the Jeopardy match, but consumed 3-4 kW vs the 20W of brain power used by the two human competitors.

Strained silicon and III-V channels

Straining semiconductor material within a transistor increases the mobility of the electrons flowing through it, leading to either faster or lower-power devices than could be built with unstrained silicon.

As transistors shrink to nanoscale dimensions, however, variability in performance is growing and high manufacturing yields are getting harder to achieve. According to reports provided in advanced of the VLSI Symposium, to be held June 12-15 in Honolulu, two main reasons are atomistic doping effects (i.e. the discreteness of doping becomes important in devices with nanoscale dimensions) and manufacturing-process-induced variations. In transistors for low-power applications, thin-body structures have been shown to suppress off-state leakage current without the need for doping, and also to reduce sensitivity to gate-length variations. But whether these benefits can be achieved for high-performance applications is unclear, because it is difficult to strain thin-body structures effectively to enhance performance.

At the VLSI Symposium, IBM Alliance researchers will describe how they managed to do this for transistors at the 22nm CMOS technology node. The strain was enabled by in-situ-doped raised-source/drain (implant-free) and strained-channel processes. The devices achieve record-high transistor drive currents at given off-currents. The researchers say these strain engineering techniques are extendable to even smaller transistors.

Figure 3. Cross-sections of common types of device structures build with III-V channels. Source: Shinichi Takagi, University of Tokyo.

However, still higher electron mobilities are required to enhance transistor performance at lower supply voltages. Figure 3 shows several different "flavors" of transistors with III-V channels that offer this high-mobility.

At IEDM, an Intel-led team unveiled tri-gate FinFET-type quantum-well InGaAs MOSFETs with 30-nm gates that deliver the best electrostatic performance of any III-V MOSFET. Two key metrics are subthreshold slope and drain-induced barrier lowering, or DIBL. Long-channel devices exhibited a subthreshold slope of 66 mV/decade, close to the theoretical minimum of 60 mV/decade, while DIBL of short gate length devices was significantly improved over best-in-class planar III-V MOS devices. At the upcoming VLSI Symposium, University of Tokyo researchers will report the first sub-60nm III-V n-channel MOSFETs on silicon substrates with excellent control of short-channel effects and suppression of off-state leakage current. The devices, which are made from InGaAs- and InAs-on-insulator on silicon substrates, enable higher transistor on-state current thanks to carrier mobility enhancement and to reduction of parasitic resistance.

Beyond 10nm

With current scaling approaches, gate lengths as small as 10 nm are likely to be achieved. But is that the end? A Purdue-led team decided to try to find out. Through atomistic simulations, they looked at several promising device designs and material combinations: carbon nanotubes, graphene nanoribbons, and III-V and silicon ultra-thin-body devices and nanowires (graphene is a one-atom-thick sheet of carbon atoms with an exceptional set of properties that give it great potential for electronics applications). They performed extensive numerical simulations of intrinsic characteristics, limiting factors and design impacts. The simulations show that a) with careful engineering, good sub-threshold swing can be obtained for many of these device alternatives for gate lengths down to 8 nm; b) non-planar devices can provide good performance even at 5-nm gate lengths; and c) when the bandgaps are the same, carbon nanotube FETs and small-diameter silicon and III-V nanowires exhibit roughly the same performance, but the details of the potential profile and the onset of interband tunneling are critical.

Figure 4. The ultimate 3D transistor might be a silicon nanowire with the gate wrapped entirely around it. The dots in the left-most image are individual atoms. Source: IBM.

In recent work, IBM used synthesized graphene to produce record radio-frequency (RF) performance from transistors (reported at IEDM 2011). The IBM team demonstrated a 280-GHz cut-off frequency in a 40-nm gate-length FET, the fastest ever reported from synthesized graphene. They also achieved record high output current (5 mA/??m) and transconductance (2 mS/??m) in synthesized graphene FETs (albeit with longer gate lengths), and explored the impact of gate dielectric selection. These devices also demonstrated an appreciable RF voltage gain of 10 dB.

The first experimental demonstration of sub-10-nm transistors made from carbon nanotubes (CNTs) was also conducted by IBM. The CNT-based transistors not only demonstrated better current-drive performance than conventional silicon devices under similar bias conditions, they performed better than theory predicts they should have. Single-walled CNTs are a possible replacement for silicon but it hasn't been clear that sub-10-nm gate length CNT-based transistors can avoid short-channel effects that degrade performance. The IBM researchers have shown that such aggressively-scaled CNT-based transistors are, in fact, feasible. They built devices that achieved more than four times the current density (2.41 mA/??m) of the best competing silicon device, at a low operating voltage of 0.5 V. The researchers speculate that theoretical predictions were exceeded because the transistor gate modulates the charge not only in the channel but in the contact regions as well, which had not been considered previously.

As exciting as the potential of new materials may be, IBM's Bernie Myerson, speaking at ISS earlier this year, sounded a cautionary note. "There are carbon nanotubes, and people have made transistors out of them. But when you really get serious about making these things into technology, you really have to start looking at the genuine dimensions you want to use them at, what you're going to do with them and how they're going to behave. It's really great to see all these picture where people make a device and they get some numbers from them, but you have to make about 10 billion of them work to be competitive with current silicon. ???


1. Mark Bohr, "The Evolution of Scaling from the Homogeneous Era to the Heterogeneous Era," IEDM 2011, p. 1.1.1.

Solid State Technology, Volume 55, Issue 5, June 2012

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