The Micron Memory Cube consortium


Micron has joined with Samsung to create the "Hybrid Memory Cube (HMC) Consortium" with fellow founding members Altera, Open Silicon, and Xilinx. IBM will be manufacturing the the logic layer.

The consortium is built around Micron's hybrid (previously referred to as "hyper") memory cube technology. The initial goal of the consortium is to define specifications for HMC. The HMC interface is totally different, having nothing in common with current DDR implementations, so it is felt that standardization and adoption by major producers and users is the only way that HMC will become a standard memory product for the industry.

Memory bandwidth required by high-performance computers and next-generation networking equipment has increased beyond what conventional memory architectures can provide. The term "memory wall" has been used to describe the problem. A solution to the memory wall problem requires an architecture that can deliver increased density and bandwidth at significantly reduced power consumption.

While DDR DRAMs have gotten bigger through the years by increasing the parallel arrays of DRAM cells on chip, they remain limited to the bandwidth supported by package I/O. DDR3-1333 and DDR3-1600 devices currently offer bandwidths of 10.66 Gbps and 12.8 Gbps respectfully. The HMC is a stack of multiple memory die sitting atop a logic controller chip bonded together using TSV. This greatly increases available DRAM bandwidth by leveraging the large number of I/O pins available through TSVs. Both the number of contacts and their shorter lengths enable dramatically higher data transfer rates than today's memory other memory architectures ??? Micron has shown prototypes rated at 128 Gbps.

Current DRAM burns a huge amount of the power in laptops and phones. Brian M. Shirley, VP of DRAM solutions at Micron, claims that the company's hybrid memory cube technology "offers a 20-fold performance increase while reducing the size of the chip and consuming about one-tenth of the power," while occupying 10% of the volume of a DDR3 memory module. Micron reports that the HMC module achieves and exceeds 128 Gbps by using parallel channels.

Joe Jeddeloh, whose Micron team developed the logic portion of the HMC has described the key "themes" of their technology as follows: "Instead of a DRAM die being one large device that has one set of I/Os on it, we break it into, say, 16 separate DRAMs, in essence much like a multicore processor. Each of those DRAMs has its own interface so when you go to access data, you go to a very local area of DRAM. It's a more directed access. Then, we move that down the Z direction on a TSV."

Micron recently announced that they will be manufacturing the memory layers and have contracted with IBM to manufacture the logic layer. Micron will be doing the assembly of the layers at a yet to be disclosed location. The technology described by M. G. Farooq of IBM last December at the IEEE IEDM is the technology being used to create the logic layer in the HMC stack (the blue layer in the illustration, Source: IBM).

Solid State Technology, Volume 55, Issue 4, May 2012

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