Accelerating high-k dielectric solutions for next-gen DRAM capacitors


Executive Overview

This article describes a program to accelerate the development and optimization of a Zirconium (Zr) high-k dielectric solution for next-generation DRAM capacitors. The program yielded a solution that offered 10% improvement in capacitance and a 10x reduction in leakage.

John Doering, ATMI, Tempe, AZ USA, Weimin Li, ATMI, Danbury, CT USA

The tremendous R&D outlays required for advanced technology nodes pose a serious challenge to today's integrated device manufacturers, who also face economic uncertainty. Much time and money goes into finding new materials and new processes required to make the smaller devices that perpetuate Moore's Law and still deliver the more energy-efficient results desired today. Process technology costs are a particular challenge – in logic technology, the move to 22nm, for instance, encompasses 45 new materials and more than 1,000 process steps. In memory, new process flows incorporating copper wiring encompass over 500 process steps.

Yet, in our industry, new materials development has remained a relatively slow and resource-intensive process involving four discrete stages (materials R&D, unit process R&D, process integration and device performance optimization). These steps have traditionally been performed sequentially, and it's not unusual for the entire sequence to take 1-2 years and cost tens of millions of dollars. Those kinds of timelines and expenses are simply not sustainable, particularly in memory where margins are continuously shrinking.

Collaboration and rapid screening

In 2008 ATMI launched four High Productivity Development Centers around the world that promote collaborative approaches and include Intermolecular's Tempus R&D Platforms to help accelerate development and integration of new materials and processes. High-productivity development for deposition technology spans four broad areas of R&D. They are:

• Determining film composition in the early days of device design;

• Screening the best precursor for film deposition;

• Identifying the optimal process window using that material; and

• Helping scale that process up in a high-volume manufacturing environment.

Combinatorial methods are used for film-composition study, precursor screening and process-window optimization. This enables us to collaborate with end users on their needs, work together to assess many different materials simultaneously and arrive at an optimal precursor at a fraction of the time and cost previously required—and with much more data than traditional R&D approaches. The high speed of discovery and substantial acquired data help shorten time-to-market for new devices and improve confidence in the output.

Using this new approach, the aforementioned tasks need not be organized sequentially – instead, they are separated into roughly concurrent primary, secondary and tertiary screening phases—also known as massive parallel processing. This means that earlier phases can be conducted on small areas of relatively inexpensive blanket substrates, so many experiments take place at the same time. Only candidates that meet specific, pre-determined criteria are moved to secondary and tertiary phases, where candidate materials can be tried on increasingly more complex test wafers – up to and including full-patterned wafers suitable for reinsertion into manufacturing and subsequent process steps that allow for highly representative process integration results. This helps a team quickly focus on only the most promising possibilities, and arrive at the optimal process faster and with vastly more information.

A new dielectric for next-generation DRAM capacitors

ATMI recently teamed with development partner Intermolecular to accelerate the development and optimization of a Zr high-k dielectric solution for next-generation DRAM capacitors.

DRAM manufacturers face several challenges; among them, shrinking cell sizes, an expected rash of new materials and rapid reduction in prices over a product lifecycle. According to the ITRS International Technology Roadmap for Semiconductors (ITRS), 2009 Edition, "DRAM capacitor technology is now more seriously challenged than any other previous period due to the accelerated scaling of cell size…. As cell critical dimension decreases down to 20nm, the most difficult situation faced is that there will not be enough space for the deposition of the dielectric layers and the plate electrode because of an extremely limited area [1]." Maintaining the capacitance with smaller surface areas normally involves thinning the dielectric film that impacts leakage. Minimizing both equivalent oxide thickness (EOT) and leakage is essential.

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Table 1. ITRS DRAM roadmap. SOURCE: International Technology Roadmap for Semiconductors, 2009 Edition

To reduce both EOT and leakage at the same time, the ITRS predicts that new capacitor dielectric and electrode materials will be required in the coming years (Table 1). Each material change requires new precursors for depositing film on the die. Thus, for each subsequent generation of DRAM technology, manufacturers must develop new precursors for high-step coverage ALD process to compensate for device and capacitor shrinkage. But with margins declining, large R&D outlays just don't make economic sense.

Even when new technology nodes use the same dielectric material as the previous generation, the increased aspect ratio of the capacitor structure puts a stronger requirement on step coverage of the ALD process. Improving the precursor is one way to meet the challenge of achieving better capacitor performance.

TEMAZ has been the precursor of ALD ZrO2 processes used in 5x nm DRAM capacitors. As DRAM is moving from 5x nm to 4x nm and 3x nm technology nodes, DRAM manufacturers are phasing out TEMAZ-based processes and seeking a more effective precursor. Using traditional methods, one DRAM manufacturer had evaluated most of the available Zr precursors without finding a suitable replacement. ATMI had developed one, TCZR, which demonstrated improved performance on leakage, but equivalent performance on EOT. The DRAM manufacturer believed better precursor candidates existed but could not afford to spend another 20 months evaluating them using conventional methods.

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Figure 1. High productivity development approach for precursor development process for DRAM capacitor. SOURCE: ATMI/Intermolecular.

Using high-productivity development tools and techniques, we were able to follow the same evaluation process (Fig. 1) that the manufacturer initially followed, spanning:

• Precursor synthesis and basic characterization;

• Unit process, MIMCAP data and scale up; and

• Step coverage and DLI wdemonstration.

Process characterization involved evaluating each candidate on the basis of vapor pressure and viscosity. Candidates that passed the screening criteria were then moved on to unit process screening, where we considered the additional criteria of saturation, temperature window and structure. By that point, the initial pool of 12 candidates had been reduced to just one – the chemistry EZr. The next step was to evaluate EZr against TCZR and TEMAZ on the basis of EOT and Jg (a measure of capacitor leakage). Finally, the team evaluated each candidate's ability to scale up in production.

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Figure 2. Comparison of accumulated cycle of learning between TCZR, which was characterized using traditional methodology, and EZr, which was developed using high productivity development methodology. SOURCE: ATMI/Intermolecular.

At the end of the process, We found that EZr demonstrated the best performance, with EOT reduced by 10% and Jg reduced by 10x (Fig. 2) as compared to the incumbent chemistry, TEMAZ. EZr also showed better ALD performance with up to 20% better step coverage than TEMAZ in 4x nm DRAM capacitor structures. These results met the DRAM manufacturer's stringent process requirements and ITRS specifications. Moreover, the entire process took just 16 weeks and generated as much learning data as the manufacturer's previous conventional 20-month evaluation cycle (Fig. 3).

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Figure 3. EOT comparison among three precursor candidates; EZr was shown to have the best performance. The shaded area indicates performance meeting ITRS's specification of 45nm DRAM capacitor performance.

A new, more sustainable R&D model

According to David Lazovsky, CEO of Intermolecular [2], "Time to market with superior device technology drives competitive advantage and market position for all memory companies. The ability to accelerate cycles of learning for new materials integration – spanning materials/precursor screening, unit process development, and device electrical characterization – is a key factor in bringing next-generation memory products to market faster. High productivity development methods and collaborative development models have been proven to significantly improve R&D efficiency and effectiveness."

As this DRAM capacitor project demonstrates, high-productivity development techniques can help remove much of the cost and time from the R&D cycle while improving the quality of the outcome. In the memory space, that can mean the difference between first or fourth to market – and being first, even by a month or two, results in much higher margins, commanding market share and significant revenue gains.


The impact of the high-productivity development approach will be amplified for next-generation devices, where film composition also needs to be determined. Applying high productivity development across the lifecycle – from film composition selection through to manufacturing scale up – could take years off the process.


1. International Technology Roadmap for Semiconductors, 2009 Edition, Front End Processes, p. 6.

2. Email exchange between David Lazovsky, CEO of Intermolecular, and article co-author John Doering of ATMI on March 30, 2010.


John Doering earned a BSEE from U. of California, Berkeley and an MS in mechanical engineering from Stanford U. He is director of deposition technologies at ATMI, Tempe, AZ. ph: 480-736-7609, email:

Weimin Li received his BE degree in materials science and engineering from Tsinghua U., Beijing, China and a PhD in semiconductor materials from the University of Utah. He is deposition technologies product manager at ATMI.

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