Comparing SOI and bulk FinFETs: Performance, manufacturing variability, and cost


Executive OVERVIEW
This article compares the performance, process variability, and cost of speculative FinFET process flows based on SOI and bulk silicon substrates. While both SOI and bulk FinFETs should be able to achieve comparable performance, a bulk FinFET fabrication flow will require more process complexity. In SOI wafers, the buried oxide layer isolates individual transistors, while in bulk devices, isolation must be created by the wafer process. We show that, because the bulk FinFET process is more complex, it will lead to 140-160% more device variability, and thus to significant manufacturing and process control challenges. Though SOI substrates are more expensive, the costs of the more complex bulk FinFET process largely offset this expense, resulting in a roughly equivalent cost basis with bulk at production volumes.

Horacio Mendez, SOI Industry Consortium, Austin, Texas, USA; David M. Fried, IBM, East Fishkill, NY USA; Srikanth B. Samavedam, Freescale Semiconductor, East Fishkill, NY USA; Thomas Hoffmann, IMEC, Leuven, Belgium; Bich-Yen Nguyen, Soitec,Austin, Texas, USA

As the semiconductor industry looks toward the 22nm technology node, some manufacturers are considering a transition from planar CMOS transistors to the three-dimensional (3D) FinFET device architecture. Relative to planar transistors, FinFETs offer improved channel control and, therefore, reduced short channel effects. While the gate in a planar transistor sits above the channel, the gate of a FinFET wraps around the channel, providing electrostatic control from both sides.

Challenges of a 3D structure

The 3D structure introduces new parasitic capacitances and new critical dimensions that must be controlled to optimize performance. The gate length in a FinFET is measured parallel to the length of the fin, while the gate width is the sum of twice the fin height plus the fin width. Fin height limits the drive current and the gate capacitance, while fin thickness affects threshold voltage and short channel control, as well as contributing to second order metrics such as power consumption.

In a 22nm node device, fin width might be on the order of 10-15nm. Fin height would ideally be twice that or more—increasing the fin height increases the transistor density, allowing more effective gate width to fit in a smaller planar footprint. As we will discuss, however, taller fins make both the fin etch and, for bulk FinFETs, the recess etch and isolation implant more difficult.

Controlled manufacturing of a 3D structure with such small features presents new process control challenges. The trench etch that creates the fins must maintain a vertical profile with minimal sidewall roughness over a 2:1 or greater aspect ratio. Variability and yield are important considerations as manufacturers decide which process flow to adopt.

This article analyzes the performance, variability, and cost of two potential FinFET process flows—one based on silicon-on-insulator (SOI) substrates, and one using bulk silicon substrates with an implanted junction for fin isolation.

SOI-based flow. The SOI-based flow is the most straightforward. The fin etch simply stops on the wafer's buried oxide layer; the fin height is defined by the initial SOI layer thickness. Moreover, because of the buried oxide layer, adjacent fins are fully isolated from each other and no additional isolation steps are required. In the fully-depleted, undoped-channel devices being considered for this node, only gate fabrication and source/drain implants are needed to complete the device.

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Figure 1. Process flow for bulk FinFET with junction isolation.

Bulk silicon-based flow. In contrast, when a bulk silicon substrate is used, there is no clear demarcation of the base of the fin, and no inherent isolation layer. Instead, the process must manufacture transistor isolation. In a junction-isolated flow (Fig. 1), the fin etch is followed by an oxide fill step. The oxide deposition must fill a deep, high aspect ratio trench, without voids or other defects. Polishing the oxide back to the silicon sets the fin height, then a recess etch clears the space between fins. This recess etch, like the initial trench etch, has no obvious stop layer—etch depth depends on etch time, and is subject to microloading effects as the fin density varies through the design space. Though the oxide provides insulation between adjacent fins, the transistors are still connected underneath the oxide. A high-dose angled implant at the base of the fin creates a dopant junction and completes the isolation.

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Figure 2. Process flow for bulk FinFET with material isolation.

Material-isolated flow. Some research has also considered a material-isolated flow (Fig. 2), in which a hard mask spacer protects the sides of the fin while oxide is allowed to grow from the oxide trench isolation across the bottom of the fin. In this process, the degree of oxide growth depends on the growth time—all fins must have the same thickness to ensure complete isolation. The oxide isolation growth process is inherently difficult to control, and the flow adds several process steps relative to the junction-isolated flow. Because of its complexity, we do not believe that the material isolation approach will be viable for manufacturing, and have not included this flow in subsequent analyses.

SOI and bulk flows offer matched performance

Relative to DC performance, SOI and bulk-based FinFETs achieve comparable on/off current ratios for matched device dimensions [1]. Differences begin to appear when considering such parameters as junction leakage and parasitic capacitance. Here, the oxide ground plane intrinsic to SOI makes the 22nm node's performance targets more achievable.

As described above, isolation in junction-isolated FinFETs is provided by a high-dose (1018/cm3) dopant layer at the base of the fin. This layer can be implanted either before or after the recess oxide deposition and etch; however, alignment between the junction and the oxide layer is critical. Its impact on device performance is similar to that of spacer-channel alignment in planar transistors.

Performing the implant before the recess oxide deposition and etch would amplify the impact of non-uniformities in the already challenging recess etch step. Instead, most process flows being considered for commercialization perform the oxide deposition and etch first, using the oxide layer to align the junction implant. Even in this process order, optimizing implant conditions to provide appropriate dopant junctions at the base of the fin is quite challenging.

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Figure 3. Transistor matching for SOI-based FinFETs, bulk silicon-based FinFETs, and planar transistors [2].

Implants produce a dopant gradient, even under the best circumstances. It's difficult to implant sufficient dopant at the base of the fin producing a gradient in the body of the fin. While SOI and bulk FinFETs can achieve comparable leakage performance, random dopant fluctuations in the bulk FinFET will affect transistor-matching characteristics (Fig. 3). SOI-based devices have no junction isolation implant, and so are not subject to this effect.

The differences between junction isolation and SOIs buried oxide also affect parasitic capacitances. Because of their design, all FinFETs are more prone to parasitic effects than comparable planar devices [3]. The buried oxide layer helps minimize capacitance for SOI devices, while junction-isolated bulk devices suffer from the capacitance due to the junction. As fin height increases, however, the total capacitance increases and the contribution of junction capacitance becomes less dominant. For fin height greater than 40-50nm, junction capacitance imposes a 5-6% ring oscillator penalty.

Reducing variability

Though candidate processes can be identified based on performance considerations, the "best" process might vary significantly depending on the design. A high-performance design might be less concerned about overall cost, and more concerned about variability and variability reduction. A low-power commodity chip might be most concerned about leakage and power consumption,but might be extremely cost-sensitive. Rather than attempt toaddress these issues, our analysis focuses on the variability andcost of a simplified generic process.

From a cost and variability standpoint, our model can be seen as a best case: it considers only digital circuit elements, with a single threshold voltage. It assumes only one fin pitch—a probable scenario, as manufacturers are likely to adjust transistor dimensions by adding fins to a given device. Using a single fin pitch simplifies lithography and etch—an important consideration as both processes are likely to be challenging at the 22nm node.

More realistic devices are likely to see additional costs and increases in the number of process steps. Additional threshold voltages will add implant masks, while additional metal layers will bring more metal deposition, patterning, and polishing steps. We hope readers will be able to evaluate their own processes within the framework we provide.

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For the variability analysis, we assumed that SOI and bulksilicon-based FinFETs will use similar toolsets. We don't expect the SOI trench etch to achieve tighter tolerances than the equivalent bulk process step, for instance. We also assumed that process improvements over time will benefit both toolsets equally.

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The additional process steps required for bulk FinFETs, however, impose a substantial variability penalty. In the SOI-based flow (Table 1), the most important sources of variability are the substrate itself (which defines fin height) and the fin etch verticality and sidewall quality. Bulk FinFETs (Table 2) suffer from fin etch variability as well. In fact, the need for additional oxide isolation means that fins must maintain their vertical profiles with even higher aspect ratios. Moreover, neither the fin etch nor the recess oxide etch can depend on an intrinsic stop layer comparable to that provided by an SOI wafer's buried oxide. These are timed etches, with all the vulnerability to process variation and microloading effects that implies. Finally, as discussed above, controlling the junction isolation implant is likely to be extremely difficult.

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Not only are the bulk FinFET process steps likely to be more highly variable, but there are numerically more of them. As Table 3 shows, our model SOI flow requires 56 process steps, while the junction-isolated bulk flow requires 91, including two additional mask layers. Even if all the steps were equally variable, bulk FinFETs would face more process variability. In our model, we expect bulk FinFETs to see 140-160% of the variability of SOI-based devices (Table 4).

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The additional process steps impose a similar burden on process cost (Table 3). We estimate that by 2012, the cost of SOI substrates will fall to $500, due to increasing use of these substrates in volume manufacturing. Though SOI substrates will remain more expensive than bulk silicon wafers, their contribution to the total process cost decreases as the total cost per wafer increases. Even for our model flow, the net cost increase for SOI FinFETs is only $136 per wafer. For more realistic processes, we expect the cost difference between bulk and SOI to be within the margin of error of this study (Fig. 4).

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Figure 4. Total cost difference between SOI and bulk FinFETs, relative to totalwafer cost.


This study evaluates performance, variability and cost differences between FinFETs fabricated with junction isolation on bulk silicon wafers, and FinFETs fabricated on SOI wafers. Our analysis shows that bulk and SOI wafers are, for all practical purposes, equivalent in performance and cost; however, bulk-based FinFETs are much more challenging to manufacture due to increased process variability. The higher variability associated with bulk wafers can lead to end product unpredictability. We found that the two process schemes delivered comparable DC and AC performance. Junction-isolated FinFETs do suffer from a small increase (5-6%) in parasitic capacitance.

In contrast, process variability comparisons show that SOI FinFETs are likely to have superior matching characteristics.Fin height and width are likely to be more easily controlled inthe SOI process, while the bulk process faces significantmanufacturing and process control challenges.

At the 22nm technology node, density scaling expectations are such that FinFETs begin to offer tangible advantages over planar technology.

First, contacted gate pitch must shrink to a point of constraining gate length below any channel length demonstrated for high-performance transistors. The inherent short-channel advantages of FinFET may allow this scaling, without the deleterious effects of massive channel doping required by planar devices.

Also, SRAM bitcell area expectations have begun to dictate variability requirements of the individual transistors.  Undoped-body FinFETs, as has been the focus of most research, would remove the random dopant fluctuation (RDF) component of device variability. This reduction may be essential for achieving low operating voltages in high-performance SRAM bitcells.

SOI-based FinFETs suffer a modest cost penalty, due to the increased substrate cost. At high volumes, this is largely offset by the cost of the more complex bulk process.


1. B. Parvais, et. al., "The Device Architecture Dilemma for CMOS Technologies: Opportunities and Challenges of FinFET Over Planar MOSFET," 16th Intl. Symp. on VLSI Tech., Systems, and Applications, Hsinchu, Taiwan, 2009,(VLSI-TSA 2009). 

2. T. Hoffman, "Perspectives on Technological Opportunities & Challenges of Multi-Gate Non-Planar Device Architectures," Intl. Workshop on INSIGHT in Semi. Dev. Fabrication, Metrology, and Modeling, Napa, CA, 2009,(Insight 2009). 

3. M. Guillorn et al., "FinFET Performance Advantage at 22nm: An ACperspective," Symp. on VLSI Tech., Digest of Tech. Papers, pp. 12-13, 2009, (VLSI-2009). 


Horacio Mendez received his Bachelors degrees in mechanical engineering and materials science and Masters in semiconductor physics from the U. of Texas, and is executive director at the SOI Industry Consortium, 1010 Land Creek Cove, Austin, TX 78746 USA; 512-992 1809;

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