QFN Package

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SiP technology placement of two or more die in a single package makes this stacked-die QFN-MCM package ideal for portable consumer devices. A 0.9-mm package height with a 7-mil minimal die thickness (2-die pyramid stacking one die side-by-side) saves board space, increases package efficiency in the Z-direction, and provides a short electrical path for high reliability. An exposed leadframe pad provides a direct path for removing heat from the package. The QFN Package is green-compliant and qualified to MSL 260C. Advanced Interconnect Technologies, Sunnyvale, CA,

Polishing Template

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This polishing template employs a “shim spinning” feature that assures maximum adjustment flexibility of the wafer protrusion, controls wafer thickness variations, and allows the wafer to spin freely in the pocket or cavity. The spinning dynamic results in an even wafer surface; significantly improving TTV, bow, and warp. Designed for silicon, germanium, gallium arsenide, quartz, sapphire, silicon carbide, and other substrates, the template is able to withstand high temperatures, pressures, and high polishing speeds, and provides effective slurry flow/distribution for all CMP processes. ZeroMicron Inc., San Jose, CA,

Silicone Gap Filler

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ThermaCool TC 3000 gap filler provides thermal conductivity in demanding applications such as power supplies and power electronics. Designed for UL 94 V-O flame rating, it employs flame-retardant packages with no halogen compounds. It adheres to a wide range of materials, yet is easily repositionable, and can be supplied with either a film or a special coating to eliminate any tack on one surface. Available in two different durometers to give soft or very soft compliance, it is produced in thicknesses from 20 to 250 mils. Saint-Gobain Performance Plastics, Worcester, MA,

MEMS Chamber

The Environmental MEMS Chamber allows full control of environmental conditions while performing in-plane and out-of-plane stroboscopic interferometric microscopy. It conducts electrical and mechanical testing for environmental parameters such as temperature (-25° to 65°C), varying gases, or vacuum to 10-6 mbars. Analysis options include real-time video of measurement, real-time vector analysis, and average displacement over the entire area or defined areas of study. The chamber is available as an option on the Photomap 3D or Zoomsurf 3D with an optional dynamic characterization module for in-plane and out-of-plane real-time vibration mode studies from 100 Hz to 2 MHz. Micro Photonics Inc., Allentown, PA,

Wafer Prober

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The Pureline wafer prober line provides the tools for low-level, on-wafer measurement capability in device characterization and modeling, wafer-level reliability, and yield enhancement. Integrated features include a MicroChamber shielded wafer enclosure for reduced EMI and RFI interference; an AttoGuard active guard for reduced stray capacitance and noise reduction; low-noise triaxial thermal chucks for suppressed noise injection; and low-impedance grounds for improved bypass of broadband transmissions. Designed to offer measurement immunity from electrical background transmissions, Pureline allows low-level measurements on sensitive semiconductor devices. Cascade Microtech Inc., Beaverton, OR,

CSP Socket

The 775 series surface mount, 0.5-mm-pitch CSP sockets accommodate higher-pin-count and larger-substrate CSPs. Z-axis buckling-beam contacts manufactured using a metal stamping process eliminate issues associated with small solder balls and tweezer-type contacts. Offered in a small footprint, they incorporate Retention Arm Technology, and can be used for both eutectic and lead-free solder balls. Features include low actuation force, low contact resistance, open-top construction for auto-loading applications, package-handling capability up to 16 x 16 mm, and a 30 x 30 grid matrix. WELLS-CTI, Phoenix, AZ,

Metrology Tool

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The Mentor OC23 tool measures material characterization properties to determine whether device manufacture process steps are operating correctly, shaping process changes after deposition, wet or dry etch, or CMP processing. With its non-destructive measurement on production wafers, the small footprint can directly assess if a process has been carried out successfully from Statistical Process Control (SPC) methodology. Nanotechnology weight measurement can be used on product, test, and blanket wafers independent of substrate size or material. Fully automatic cassette-to-cassette operation uses industry-standard 200- and 300-mm open cassettes to allow wafer measurements. Control of ambient conditions within the measurement enclosure provides <0.04-mg weighing capability. Metryx Ltd., Bristol, UK,

No-clean Solder Paste

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Halide-free, no-clean Multicore MP218 solder paste interacts with lead-free device finishes, and is comprised of similar raw materials, activators, and other components as those used in next-generation lead-free solder pastes. It avoids humidity-related problems of premature drying and excessive moisture absorption, enabling consistent, global performance. An anti-tombstoning formulation extends the liquidus time of solders during reflow, increasing the wetting window for each end of the component, and reducing possible tombstoning defects to enable effective joint formation. Henkel Electronics Group, Irvine, CA,

Polishing Pad

The VisionPad VP3100 polishing pad provides planarization capability and low defectivity during volume production of copper (Cu) wafers; enhancing throughput and reducing overall cost of ownership at the 65-nm node. A polyurethane formulation provides a soft surface to reduce defects while maintaining necessary rigidity. The advanced pad technology minimizes scratches and chatter marks across the wafer; improving die yields. The pad also can be conditioned to regenerate the surface and achieve optimal polishing results. It also can backfill into current 90- and 130-nm processes. Rohm & Haas Electronic Materials, Philadelphia, PA,

Cluster Platform

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The CPX cluster platform enables multiple process chambers to share a common wafer transport chamber, supplying up to four STS plasma processing modules and reducing overall cost by reducing fab footprint and operator and equipment costs. Features include a Brooks Marathon Express MX600 automation platform for wafer transport, an advanced PLC control system, twin vacuum cassettes for 25 wafer cassette-to-cassette operation, and integrated wafer alignment. Surface Technology Systems plc, Newport, Wales, UK,

3-D Metrology Systems

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Falcon 800 advanced measurement and metrology systems inspect bumped wafers to ensure bumps meet tight dimensional tolerances. Proprietary CTS triangulation height measurement technology enables broader angular coverage to create a stronger, more stable reflection from many bump shapes and materials, and supports real 3-D bump geometry reconstruction. Selected high-grade-certified mechanical structures and assemblies provide stability for micron-level measurement at high speeds. Falcon 800 also can be equipped with the Confocal Chromatic Sensor (CCS), a submicron height sensor that verifies critical height dimension or samples gold-bump surface roughness or profile. Built-in NIST-certified calibration targets are available for ensuring measurement accuracy. A comprehensive suite of SPC charts and reports supports bump defect and dimension analysis by die wafer and lot levels. Camtek Ltd., Migdal Ha’Emek, Israel,

Flip Chip Design Software

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JupiterIO, a part of the Galaxy design platform, targets flip chip design flows. Rapid delivery of chips with high bandwidth, speed, and I/O count is driving the increase in flip chip units. JupiterIO builds upon JupiterXT floorplanning to extend concurrent optimization within the Galaxy design platform for packaging impacts on finished device performance, cost, and time-to-tapeout. JupiterIO supports a package-influenced methodology that uses system and package constraints as a start-point to chip-level floorplanning, and simultaneously accesses both chip and package databases, facilitating real-time tradeoff and evaluation of key components of the die and package interface. This feature eliminates the delay and iterations associated with traditional, non-concurrent flip chip flows that rely on static post-floorplanning data for I/O and package design. Synopsys Inc., Mountain View, CA,

SMT Ceramic Packages

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These leadless ceramic SMT packages for direct PCB mount are up to .75 in2 in size, and incorporate wraparound interconnections, plugged via holes, hermetic-filled vias, and integrated passives for high circuit- and power-density applications. The packages also incorporate Plated Copper on Thick Film (PCTF) technology, which comprises ductile plated copper over thick film on a ceramic structure to help minimize solder-joint stresses during assembly. Plugged hermetic via holes with >1-mΩ resistance provide for low RF losses below .1 dB at 4 GHz for ground and signal connections. The vias’ <200 W/M x °C thermal conductivity results in a low thermal resistance path for optimal thermal management. The packages are compatible with all standard soldering, high-temperature die attach, welding, and wire bonding techniques. Remtec Inc., Norwood, MA,

Substrate Printing System

The Digital Web Press (DWP) is a high-speed system for printing digital data on flexible substrates, enabling variable length runs of any given image and supporting changing images on-the-fly. This narrow web ink-jet system is meant for applications requiring short or variable production runs of non-repetitive patterns or precise metering of conductive inks. It uses various specialized, flexible substrates for color and monochromatic label printing and electrical applications, such as RFID tags. The system minimizes web weave and speed variations to maximize image quality while running at speeds up to 150 ft/min, and features 8 to 24 print heads and print widths from 2 to 6 in. Optional ultraviolet (UV), infrared (IR), or hot-air ink curing systems are available. Controllable by one operator via a customizable color touch-screen application interface, the DWP eliminates high setup costs and long lead times. imaging Technology international (iTi) Corp., Boulder, CO,