Hybrid No-flow Underfill for Flip Chip


A Nearly Void-free Process Technology


Underfills are used in flip chip packaging to help mitigate the effects of the large coefficient of thermal expansion (CTE) mismatch between the silicon chip and the laminate circuit board. They reduce the strain on solder joints to improved interconnect fatigue life.

The conventional capillary flow underfill process involves fluxing, placing, and reflowing the flip chip, and dispensing the underfill along the sides of the chip. The underfill flows by capillary action to fill the area underneath the chip. Finally, a cure must be completed in an oven.

No-flow underfill processing uses fluxing underfills that are dispensed onto the substrate before flip chip placement. The chip is placed onto the dispensed underfill, causing squeeze flow of the material. The assembly is then reflowed and cured simultaneously in a standard solder reflow process. Problems with the conventional no-flow process include excessive underfill voiding and high CTE of the non-filled underfills.

To eliminate voiding and premature component failure due to solder extrusion into voids, a new no-flow technique has been developed (Figure 1). The new process combines the advantages of conventional capillary flow underfill and conventional no-flow underfill processes. The capillary flow dynamic allows for nearly void-free assembly. The no-flow materials allow for processing without flux, thereby reducing cost and increasing throughput capabilities. This article presents a systematic optimization of the placement and reflow parameters for this hybrid no-flow process using five commercially available underfill materials.

The Experiments

The primary goal was to develop and test the reliability of this hybrid no-flow underfill assembly process, which uses a capillary flow dynamic with an edge patterned dispense of no-flow fluxing underfill materials.

Figure 1. Nearly void-free hybrid no-flow flip chip assembly process.
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The secondary goal of the research is to provide optimized processing parameters for five commercially available no-flow fluxing underfills for the new hybrid process development. These materials were used to develop and verify the new hybrid process.

To accomplish these goals a series of experiments were conducted. The underfill dispense process experiment determined optimized underfill dispense parameters. A placement process experiment was performed to determine optimal chip-placement parameters. A line position study helped to gain a better understanding of how line pattern location affects underfill voiding. A parametric reflow study determined optimized reflow parameters.

The test dice consisted of eutectic tin-lead, solder-bumped, flip chip devices with daisy-chain test structures. The flip chips were assembled on FR-4 substrates based on a design of experiment (DOE) varying dispense pattern and placement speed for each underfill (Figure 2). These assemblies were low-temperature cured at 130ºC for 1 hour to avoid reflow and any material volatility. This way the effects of the factors included in the DOE could be studied in relative isolation from the reflow process. A summary of the voiding data is displayed in Table 1.

Dispense Process

Dispense pattern (dot-and-line), placement force, dwell time, and how each factor affects electrical interconnect yield and underfill voiding were examined for each material. The only interconnect yield failure observed was for one process condition: dot pattern, 1N placement force, 0-s dwell time. All other treatments result in 100% interconnect yield, and materials show similar characteristics. The line pattern resulted in 100% yield for all tested materials regardless of the force or dwell used, due to the relatively small placement-force requirements for die placement onto the line pattern, rather than the full force from squeeze flow under the usual dot pattern placement.

Figure 2. Underfill dispense patterns.
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The dispense pattern was a significant factor affecting the number of voids occurring during placement. It seems likely that the capillary flow process associated with the line pattern is better at filling the substrate topology and solder mask openings without capturing voids during the process. The dot-and-cross patterns result in squeeze flow that has a tendency to capture voids during the rapid flow of the material. The line pattern was selected for further experimentation because it resulted in minimal voiding.

Placement Process

Placement speed was not a significant factor affecting the number of voids occurring during placement.

The placement machine triggers the onset of dwell time after reaching the programmed placement force. After the dwell time has completed, the chip is released from vacuum. The line pattern results in an underfill pressure small enough that even with the machine set to place at 1N and no dwell time, chip release is not triggered until the chip contacts the board. When using the dot pattern with minimum force and no dwell, die release happens above the substrate, resulting in misalignment after reflow, and therefore a low interconnect yield. X-ray analysis confirmed misalignment of those assemblies that failed continuity testing.

Underfill Voiding

The voiding results for patterns follow the same trend seen in the dispense process characterization. The line pattern is the best performer in terms of void formation and interconnect yield. Some fillet non-uniformity was observed for both line and dot patterns. The fillet data was not strictly quantified, but the line pattern shows a difference in volume between the dispense side of the chip and the opposite side of the chip. However, both sides have well-shaped fillets.

Dwell time was not a significant factor affecting voiding for any material; therefore dwell time of 0.0s is used as the select process parameter. Dwell time is not critical to the line pattern, which is the pattern of choice, because the chip is placed with very little contact onto the dispensed underfill, minimizing the risk of die floating and placement shift. This makes a dwell time unnecessary to avoid release above the substrate, a possiblity with dot dispense. When considering the viability of this process for a high-volume manufacturing environment, a reduced dwell time results in better throughput and therefore is more desirable from a cost standpoint.

Figure 3. Line position study.
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The effects of placement force on voiding are mixed based on the experimental results. For two materials (A and D) force does not appear as a significant factor, while for materials B, C, and E, force appears significant with a higher force resulting in increased voiding.

Table 1. Underfill voiding results as factor-level means.
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Line Position Study
When investigating the location of the dispensed underfill line in relation to the edge of the die and substrate bond site, only one material, Material A, is used for evaluation, and the results should be qualitatively similar to the remaining materials. Figure 3 shows the line positions, with the cross-section of a dispensed line shown at position 1. All five line positions resulted in 100% interconnect yield for each part assembled. The fillet results appear to be comparable for each line position, with a small difference in fillet size for the dispense side and side opposite the dispensed line. This determines the line position threshold that produces significant underfill voiding due to material flow over the pads or by direct dispense onto the pads. Representative CSAM images for each position are shown in Figure 4.

Figure 4. Representative CSAM images for line positions 1-5.
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The position of the dispense line in relation to the edge of the substrate bond site has a clear effect on the percentage voiding of the underfill. It is clear from Figure 5 that there are regions where the line can be positioned such that no voiding is present in the final assemblies. This region extends from about the edge of the die to a location that is approximately 8 non-dimensional units to the outside of the die edge, and indicates that the capillary flow dynamic of the assembly process does not inherently produce voids as the material flows under the die. Thus, any voids present in earlier experiments are most likely due to line placement too close to the pad openings that can result in trapped air from the dispense onto pads, or to voids forming due to a partial compression flow of the material over the pads during placement.

Reflow Study

Two distinct types of reflow profiles were used in this experimental work; these types are described as either a step or a ramp profile. Due to limitations on time and materials, an optimized reflow profile was determined by conducting a parametric study.

Figure 5. Non-dimensional line position voiding results.
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The emphasis on underfill voiding as a metric for reflow optimization can be understood by considering the results of experimental failure-analysis work, which concluded that flip chip devices subjected to thermal cycling are seen to initiate delamination at the site of voids in the underfill. Once initiated, this delamination propagates along the passivation-underfill interface, ultimately rendering the underfill incapable of sufficiently coupling the die to the board, and thus to fatigue failure of the joint. Additionally, other no-flow underfill research has shown that solder extrusion will occur during thermal cycling if a flow path is present. The path of least resistance to this extrusion is into a void adjacent to the solder bump. This extrusion is undesirable, both because it can cause electrical shorting failures, and because it compromises the integrity of the solder joint from which the solder is extruded.

The decision to including a grain-size ratio metric is made based on the observation that solder cracks often propagate along the boundaries of lead-rich regions. Increasing the incidence of grain boundary transitions with the joint may maximize the fatigue life of the assemblies, preferring a uniform eutectic microstructure. The grain data is determined using an area-ratio technique, where a grid was overlaid onto SEM images and the ratio of points that fell inside of the large grain boundaries is calculated (Figure 6).

Figure 6. SEM image with grain boundaries and a partial grid overlay.
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Resistance was selected as a metric, based partly on the results of a study that demonstrated that the smaller the resistance of solder joints, the larger the shear strength. Additionally, the resistance is related to the relative contact areas between the bump and the bond pads of both the chip and the substrate. It is expected that an increase in this area will lower the measured resistance, and that this would also correspond to longer fatigue life.


The main benefit of the new process is that void-free assembly results in better reliability due to avoiding early solder extrusion failures that can result when voids bridge two bumps. This type of extrusion failure has been observed to occur by 1600 cycles, which is well below the MTTF for solder fatigue observed for these parts. The trade-off for improved reliability is that the process requires more substrate space than conventional no-flow processes. This is because the underfill is dispensed to the side of the chip site and may wet out excessively before the chip is placed, requiring an unacceptable amount of board space for implementation.

The distance that the underfill wets out onto the substrate is dependant on the linear mass density of the dispensed line. Several other patterns have been determined to perform equally well, each yielding 100% and resulting in no voiding.

A nearly void-free no-flow underfill dispense process was developed including a novel ranking methodology for improved reflow process characterization. Test assemblies produced with this process have exhibited exceptional reliability performance with all parts passing 2000 AATC cycles without any electrical failures.


Contact the authors for a complete list of references.

DANIEL F. BALDWIN, Ph.D., may be contacted at Engent, Inc, 3140 Northwoods Parkway, Suite 300A, Norcross GA; 678/990-3320; E-mail: MICHAEL COLELLA may be contacted at 602/614-4235.