DRIE for MEMS devices



MEMS products are finding more applications in consumer markets like automotive, telecommunications, information technology, health care and environment. Because they address a high-volume, yet competitive market environment, MEMS products — including gyroscopes, accelerometers, silicon microphones, ink jet printer heads, tire pressure sensors, biomedical integrated devices, etc, — need to be produced at the lowest possible cost.

Minimizing the cost of MEMS production is a key success factor for the industry. DRIE equipment manufacturers are optimizing the cost of tools and maximizing their throughput. In the case of DRIE, one important process parameter in favor of a higher throughput is the etching rate. A permanent etch rate improvement program has already produced significant progress. Process yield is also a key factor to provide the highest possible number of devices-per-wafer. Solutions like wafer bevel-edge protection and fine control of tilt profile angle have been successfully designed. A higher degree of automation is also necessary for reaching the most productive wafer handling solutions. Cluster tool platforms have been implemented to accommodate the cost-effective DRIE process modules for higher yield and higher throughput.

High Etch Rate

An efficient DRIE tool, able to produce high silicon etching rates that achieve high selectivity with respect to the photo-resist mask, requires high plasma density for a high dissociation of etching gas molecules together with a low plasma potential for high selectivity. Standard RIE systems are not the best candidates because of the inherent high DC bias voltage implying a low selectivity. Within the high density plasma (HDP) sources, inductively coupled plasma (ICP), is one of the best candidates because if its capacity to generate HDP (1011 to 1012 ions/cm-3), providing efficient gas dissociation and low plasma potential at relatively high pressure. The fluorine radicals produced in the ICP plasma are transported within the gas phase to the silicon surface where they react with the silicon to produce volatile SiF4 molecules evacuated by the pumping system according to the equation: Si(s) + 4F(g) ?? SiF4(g) + ΔG0.

Given plasma parameters settings such as flow rate, pressure, and ICP power will produce a given “F” partial pressure available for the removal of silicon. As the Si etch rate is directly proportional to the fluorine radicals reaching the substrate, hardware, as well as specific processes to produce higher quantity of fluorine radicals, has been developed.

Figure 1. Typical etched feature size and depth of MEMS and semiconductors.
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To achieve anisotropy, a sidewall passivation mechanism is added to the pure fluorine etching. A successful process is the “Bosch” process that alternates pure isotropic etching steps with SF6 plasma and passivation steps in C4F8 plasma on which deposits a thin polymer film on all surfaces. The polymer film will be removed on the horizontal surfaces during the first part of the next etching step thanks to the SF5+ ions bombardment. The etching will progress into the vertical direction with vertical walls (Figure 1).

Because sidewall passivation with the film of polymer is quite resistant, it allows the etching of a wide range of feature sizes on the same wafer. A screening design of experiment (DOE) was performed to optimize the passivation step. It illustrated the interaction between the process parameters, as well as the importance of the source power and the wafer temperature to reach the highest deposition rates. The high Si etch rate combined with the most efficient deposition step has allowed achievement of anisotropic, and etch rate higher than 50 μm/min. As the etch rate increases, the capability to control the wafer temperature becomes crucial to obtain a uniform etch across the wafer, whatever its diameter.

Among all the energies arriving at the wafer surface, the most important one is the energy coming from the chemical reaction of the silicon with the fluorine gas:

    Si (s) + 4xF (g) ??SiF4 (g) + ΔG0=385 Kcal/mol

This energy (PE) is proportional to the amount of Si removed by time and surface unit:

    PE = [Si mol/ (T x Mmol)] x ΔG0

With: Mmol: The molar mass (28g/mol), Si mol: quantity of removed Si, T: time, ΔG0 is the chemical reaction energy. Therefore, PE is directly proportional to the etch rate and the exposed area. This means that a significant increase of the etch rate requires an efficient chuck design to evacuate all the heat generated on the wafer surface.

To evacuate all this heat and achieve the best uniformity of temperature, a “P” type electrostatic chuck (ESC) with an innovative design was developed, allowing for adjustment of the temperature that affects wafer patterns. For a given process, the “P” type ESC gives a uniform temperature of ??0.15??C across the wafer, with excellent thermal conductivity.

High Yield

The etch rate is an important parameter for the equipment, but is not the only one. In fact, a higher yield allows for a decreased COO per die. Several solutions were developed to maximize yield, and improve the tool.

Figure 2. Cross section of a wafer edge without the bevel edge protection: important Si etch.
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Most of the time, use of a photoresist mask requires application of an edge bead removal to remove the photoresist layer at the edge of the wafer. The edge of the wafer is no longer protected and can be etched by plasma. For long etching times, excessive wafer thinning at the edge creates handling issues for further steps. A proprietary bevel edge protection was developed to avoid etching the wafer edge without impacting the overall etch performances in terms of etch rate and tilt (Figures 2 and 3).

Figure 3. Cross section of a wafer edge with the bevel edge protection: no Si etch.
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Elimination of the Tilt

Especially for gyroscope and accelerometer applications, etch profiles have to be precisely perpendicular to the wafer surface to keep device accuracy. It has been demonstrated that fluidic, ion, and neutral density are key parameters to achieve optimized process performances. Based on the ICP, a plasma source was developed with advanced solutions on geometry, materials, pressure, RF coupling, magnetic confinement, and gas injection. This plasma source combined with the “P” type ESC chuck offers previously unattained angle control solutions (Figure 4). In fact, the angle deviation is measured far below 0.2?? when conventional systems are given a value higher than 0.4??.

Figure 4. Angle deviation across a 200-mm wafer.
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Deep Etch with High Selectivity

Some applications (Si microphones, for example) require etches of more than 500 μm deep. For such etches, thick photoresists or even thick oxides were previously needed. But thick photoresist and oxide manufacturing can be expensive and time consuming. To reduce the overall process flow cost, specific hardware was developed that allows an increase in selectivity of 75% or more, creating a cheaper mask photolithography step.


Cost effective solutions for the production of MEMS have been presented. DRIE process solutions including higher etch rates exceeding 50 μm/mn have been disclosed. Wafer edge protection, elimination of tilt effect, and unrivaled mask selectivity (> 340 PR /Si) are successful methods in favor of higher yield that are commercially available. New hardware assemblies including a new ICP source design incorporated in new process modules are fitting the new cluster tool product range dedicated to high throughput, cost efficient production of MEMS devices. AP

MICHEL PUECH, technology and applications director; JEAN-MARC THEVENOUD, product and applications manager; and JEAN-MARC GRUFFAT, product director, may be contacted at Alcatel Micromachining Systems, 98, avenue de Brogny - BP 2069 74009 Annecy Cedex, France; +33 (0)4 50 65 75 93;E-mail:;;