Insights From Leading Edge

IFTLE 291 Samsung EM enters FO-WLP Packaging Mkt; Mold Cmpd Free FO-WLP for Sub MM ICs

By Dr. Phil Garrou, Contributing Editor

Samsung Electro-Mechanics launches IC packaging business

Reports are that Samsung EM (Electro-Mechanics), part of the Samsung Group, is entering the integrated circuit packaging business [link]

Samsung Electronics system LSI and Samsung Electro-Mechanics will join forces to staff the project and launch the business. They will transform current LCD assembly lines in Cheonnan KR into IC packaging lines. It is unclear whether they have developed full panel processing capability which many packaging OSATS have been trying to accomplish, or they will work in smaller formats.

Certainly their goal is to supply both Samsung and win the business of smartphone makers, like U.S.-based Apple. Apple recently gave a large order to Samsung’s competitor TSMC who will be using their InFO based FO-WLP packaging technology in Apples next smartphone.

Samsung EM has announced that they will be packaging power management ICs with Fan-out Wafer Level Package (FO-WLP) in their new factories.

IFTLE speculates that Samsung EM, a major provider of high density substrates also saw that FO-WLP was going to, or already has, begun to eat into their high density substrate business since FO-WLP can do the same job at a lower cost.

Plans are for the packaging factories to be operational in the first half of 2017.

Continuing our look at the 2016 ECTC

X-Celeprint & RTI Int Propose FO-WLP Free of Mold Compound for sub mm ICs

Closing out the morning for the “Advances in Fan Out Packaging” session at the 2016 ECTC, Matt Lueck of RTI Int discussed the results of their joint program with X-Celeprint.

A common aspect to all fan-out packaging is the requirement to physically assemble devices into dispersed arrays, often called reconfigured wafers, which provides the real estate needed to fan-out. Devices made in sub-mm chip sizes can impose cost and performance challenges to FO-WLP using serial pick-and place assembly technologies. RTI and X-Celeprint joined forces to develop a fan out package for sub mm IC using the X-Celeprint massively parallel assembly technology called micro transfer-printing, which is well-suited for handling very thin and fragile devices.

In their micro transfer-printing technology a polymer layer is first applied to the substrate before the assembly process, and the devices are assembled in a face-up configuration. Following the formation of the reconfigured substrates, conventional redistribution layer (RDL) and solder ball processing was performed. Two different photoimageable spin on dielectrics, HD4100 PI and Intervia 8023 epoxy,

were used as the RDL dielectrics. The fan-out package contains no molding compound and is made using standard wafer-level packaging tools.

There are potential benefits from fan-out packaging strategies that do not require molding compound. The process described here does not suffer from the “die drift” that occurs during compression molded fan-out packaging which often requires special adaptive alignment techniques. It also does not suffer from the wafer and package warpage that can occur in molding compound based fan-out packages.

Micro-transfer printing was used to assemble reconfigured wafers of devices (80um x 40um chips with a redistribution metal and six contact pads), onto 200mm wafers. After assembly, they undergo a standard wafer level redistribution and bumping process. The final fan-out package pitch on the 200 mm wafer is 1.4mm x 1.0mm with six 250 μm solder bumps. The fan-out packages were assembled and reflowed onto FR4 test boards.

In the figure below shows (A) the chiplet source wafer after partial removal of chiplets with the elastomer stamp; (B) a completed fan out package before solder ball placement; (C) close-up of the interconnect to the chi pads; (D) Final FO-WLP



Initial yields are reported to be 97%.

Two PCB test vehicles populated with 60 die each were built for thermal cycle testing. The board level thermal cycle testing was run under -40°C to 125°C. None of the die showed more than 0.2 ohm change in average resistance.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won’t automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *