Insights From Leading Edge

IFTLE 272 2015 3D ASIP Part 1: Pioneer Awards; Sony 3D stacked CIS; Latest on SPIL Acquisition

By Dr. Phil Garrou, Contributing Editor

Beginning coverage on the 2015 3D ASIP (Architectures for Semiconductor Interconnect and packaging) conference sponsored by RI Int which is the final major high density packaging conference of the year.

This years technical Chairs were Prof Mitsumsa Koyanagi from Tohoku Univ. and Rama Alipati from GlobalFoundries.

Professor Koyanagi of Tohoku University and Dr. Peter Ramm of Fraunhofer EMFT were the Conferences first recipients of the “3DIC Pioneer Award”. After more than a decade into the concerted effort to commercialize 2.5 and 3DIC technology it seemed appropriate to look back and document who actually led the way in this technically challenging effort. After significant study, 3D ASIP management were convinced that the research groups in Tohoku University and Fraunhoffer – Munich were not only the first to recognize what 3DIC could do, but also have continued their studies to this day to help commercialize this important leading edge technology.”

Pioneering award 2


Hirayama of Sony detailed their work on 3DIC based CMOS image sensors.

AS shown below, the color pixels require fewer metal interconnect layers and high voltage, lower temperatures during processing and longer anneal times whereas the logic portions of the circuit are quite the opposite needing many more layers of interconnect and low voltage, higher processing temps and shorter anneal times. It therefore makes sense to fabricate these layers separately and stack them.

sony 1

This separation of circuits and functions is shown below.

sony 2

Sony introduced this technology in 2012 and by 2015 had more than 2/3 of their shipped CIS using this method of fabrication.

sony 3 CSI shipments

In the future, Sony sees introduction of processors and memory to this stack.

sony 4

SPIL Acquisition

Digitimes estimates that more than $893MM worth of SPIL orders are moving to other OSAT companies due to the potential acquisition by ASE [link].

As we have discussed previously [see IFTLE 252 ‘ASE Makes Bid for Siliconware Shares…” ], ASE has previously acquired a 25% stake in SPIL through an unsolicited tender offer, and has launched another tender offer to buy more shares of SPIL which will bring its total ownership interest in the company to almost 50%. ASE has also disclosed its goal is to acquire the rest of SPIL shares, i.e a complete takeover as IFTLE initially projected. .

SPIL now reports that fabless “..chip vendors such as Qualcomm, Broadcom and MediaTek all try to diversify their suppliers to reduce supply risks”. Thus the other IC assembly and test services companies will benefit from ASE’s potential takeover of SPIL. SPIL points to Amkor, China-based Jiangsu Changjiang Electronics Technology (JCET) and Taiwan’s Powertech Technology (PTI) as the beneficiaries.

Consolidation of Notebook computer vendors.

Digitimes also reports that Japan-based PC vendors Sony, Toshiba and Fujitsu are reportedly finalizing talks to merge their notebook businesses into one company [link]. Post merger Sony, Fujitsu and Toshiba would account for 30% of Japan’s notebook market, compared to 29% held by the NEC/Lenovo joint venture.

For all the latest in 3DIC and other high advanced packaging stay linked to IFTLE…


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