Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Toshiba Memory Corporation has successfully used the Cadence® CMP Process Optimizer, a model calibration and prediction tool that accurately simulates multi-layer thickness and topography variability for the entire layer stack, to accelerate the delivery of its advanced 3D flash memory devices. With the Cadence solution in place, Toshiba Memory Corporation achieved 95.7 percent accuracy to silicon.
After conducting a thorough competitive evaluation, Toshiba Memory Corporation adopted the Cadence CMP Process Optimizer for its unparalleled feature set that addresses diverse layout topologies of array-based memory designs. The Cadence CMP Process Optimizer is based on a model-based approach versus a traditional, rules-based approach, which enabled Toshiba Memory Corporation to better predict complex, cumulative and long-range effects of chemical mechanical polishing (CMP) effects and CMP yield-limiting hotspots. Also, the Cadence CMP Process Optimizer allowed Toshiba Memory Corporation to perform simulations for the entire design stacks—both the transistor and routing layers—leading to improved accuracy. Toshiba Memory Corporation generated high-precision CMP models with the Cadence CMP Process Optimizer’s innovative capabilities. For more information on the Cadence CMP Process Optimizer, please visit www.cadence.com/go/ccpo.
“Advanced process technologies bring added complexities to the design process, and as a result, CMP effects have become more and more critical for us, particularly for our leading 3D flash memory solutions,” said Susumu Yoshikawa, technology executive, Memory Technology at Toshiba Memory Corporation. “We’ve been particularly impressed by the Cadence CMP Process Optimizer’s unparalleled capabilities, which enabled highly accurate modeling and analysis that we expect to improve product yield and accelerate the delivery of our flash devices.”
The Cadence CMP Process Optimizer offers feature-scale topography prediction and advanced reverse etch-back for accurate modeling and is part of the broader Cadence digital and signoff portfolio. From synthesis through implementation and signoff, the Cadence integrated full-flow digital and signoff tools provide a fast path to design closure and better predictability. The digital and signoff full-flow supports the company’s overall System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.