By Dick James, Senior Technology Analyst, Chipworks
July 11 â€“ 15 was the week for the annual pilgrimage down to the SEMICON West show, though itâ€™s becoming less of a show these days than a gathering place for the industry, with multiple conferences in parallel. Hence the motto for the event, “Definitely Not Business as Usual.”
Of course there were exhibitors, some 700+ Iâ€™m told, and weâ€™ll have to wait for the post-show release to see how many attendees. From my observation, things were busy without being hectic on the show floor, and there was the usual slew of press releases and social media postings from both exhibitors and attendees.
One such was a tweet from the French wafer manufacturer Soitec, which specialises in SOI wafers, having pretty well cornered the market with the success of their Smart Cutâ„˘ technology. They announced a â€śnew identityâ€ť, complete with a new logo, in time for the show and in advance of their AGM on July 25.
While I was at SEMICONÂ West I had the chance to meet with Camille Dufour and Tom Piliszczuk of Soitec â€“ we have seen increasing amounts of SOI devices in the phones that we analyze, so I was curious to find out what their range of materials was and what markets they were targeting. We have all followed the finFET/FDSOI debate in the last few years, and some still doubt that FDSOI will take off; but RFSOI and power SOI are making steady gains in the wireless and automotive sectors.
The logo change is straightforward enough:
The â€śnew identityâ€ť reflects a structural change within Soitec in the last year or two. A while back Soitec had decided to leverage their Smart Cut and Smart Stacking techniques to get into the solar cell and lighting businesses. Technologically they did quite well, getting to almost 50% efficiency for solar cells;Â but they were targeting the concentrated photovoltaic (CPV) market, which turned out to be a much more niche market than they anticipated.
Consequently the balance sheet started to suffer, to the point where some of their customers questioned the viability of the company. So at the beginning of last year the decision was taken to get out of the PV and lighting businesses, and focus on their core business of electronic materials. They also sold off their Altatech equipment subsidiary to Fogale Nanotech.
By the middle of this year all of the financial details were cleared up, and Soitec came back into operating profit. There was still a bit of a financial hangover from the discontinued operations, so a capital investment was arranged and a chunk of the companyâ€™s debt was paid off.
All of which is a roundabout way of saying that Soitec now regards itself a re-generated company based solely on the manufacture of electronic materials, so worth an announcement in time for Semicon West, the prime event for semiconductor materials suppliers.
If you peruse the products section of the website, you will see they sell four streams of SOI wafers:
- Digital SOI, which covers off partially-depleted and fully-depleted SOI (PD-SOI and FD-SOI)
- Power SOI
- Photonics SOI
Digital SOI is in a bit of a holding pattern right now; PD-SOI is in a slow decline as legacy game console parts and AMD processors fade away, and though IBM is still using PD-SOI for its Power series of processors, that is a fairly niche business and unlikely to consume huge volumes of wafers. (IBM once had the bulk of the game chip business, making chips for Microsoft, Sony, and Nintendo.)
When it comes to FD-SOI, we have seen a lot of hype, but from our perspective, no serious production yet. Soitec says that volume is now into the thousands of wafers per month, and will hit tens of thousands by the end of the year. Some products using FD-SOI have been announced, such as the NXP (formerly Freescale) i.MX 7 and i.MX 8 series of processors. Two foundries are on board, GLOBALFOUNDRIES with their 22FDX suite of processes, and Samsung with their 28 FDSOI offering; both claim multiple tape-outs are in progress (50+ for GF), and Samsungâ€™s Kelvin Low at Semicon West stated that they had shipped thousands of wafers. And both agree that FD-SOI is ideal for IoT, but again we have yet to see volume; so itâ€™s a waiting game at the moment.
FD-SOI is real, though â€“ hereâ€™s a cross-section of transistors in a Bitcoin processor chip that we looked at last year.
This was fabbed by STMicroelectronics in their Crolles fab, you can see that it is gate-first HKMG with no SiGe channel used for PMOS, as in PD-SOI. The SOI layer is ~6 nm thick, so definitely FD-SOI!
Overall PD-SOI and FD-SOI, being 300-mm wafer product, make up ~20% of sales, the remaining 80% are 200-mm wafers.
70% of those 200-mm wafers are RF-SOI, which has grown steadily due to its adoption into the RF front end of mobile phones, especially in world-phones that have to cope with more than 40 wireless bands. Soitec claim that there was 18 mm2 of RF-SOI in the iPhone 6, and 25 mm2 in the iPhone 6s, and we at Chipworks/TechInsights have certainly seen increasing amounts of SOI-based parts in the RF section of the phones that we analyze. The company asserts that 100% of smartphones have their silicon in them these days.
This (together with power SOI, which we will discuss later) has kept Soitecâ€™s 200-mm Bernin fab at full capacity for the last few months, and they expect to ship a million 200-mm wafers this year. Last year the total was 700,000 wafers, and next year they expect it to be 1.3M wafers, though some of these may be from licensees Shin-Etsu and Sun Edison. Soitec has 70% of SOI wafer sales worldwide.
Apparently there are now over ten foundries using SOI, mostly 200-mm, but Tower-Jazz has announced that its TPSCo subsidiary in Japan will be processing 45-nm, 300-mm RF-SOI, and GLOBALFOUNDRIES is now also offering 45-nm RF-SOI; I heard verbally that will be from the East Fishkill fab, but I canâ€™t find documentary support for that at the moment.
Back at the end of 2013, Soitec announced the addition of â€śtrap-richâ€ť RF-SOI technology to their product line, as an enhanced performance substrate for RF products.
As I understand it, the trap-rich layer is a layer of polysilicon formed on the handle wafer, and the multiple traps in the crystal grains and grain boundaries kill any parasitic currents that could be induced by the RF radiation, even in a high-resistivity (HR) substrate. This enables â€śRF designers to integrate onÂ the same chip diverse functions such as switches, power amplifiers and antenna tuners with excellent RF isolation, good insertion loss and better signal integrity than traditional technologies.â€ť
I was curious to see what the penetration of this new technology was into RF product lines, and was surprised when Tom told me it was 55%, and it had replaced most of the regular HRSOI wafers that they had been selling, even with a 25% cost mark-up (presumably the polysilicon process is VERY specific). He said that manufacturers were willing to pay the higher price because of the improved performance, and it also saves two mask layers. At the moment itâ€™s all 200-mm wafer sales, though 300-mm wafers are available.
As an example of the leading-edge RFSOI, hereâ€™s a SEM cross-section of a Murata/Peregrine antenna switch die from one of the RF front-end modules in the iPhone 6s:
The SOI layer is well under 100 nm thick, but we are not into FD-SOI yet, even though some claim that RF can be integrated into FDSOI! As itâ€™s a SEM image with oxide staining, we canâ€™t see if there is a trap-rich layer; that would take a different stain or TEM imaging to show it up.
Moving on to Power SOI, it is now present in 50% of cars, according to the company, with ~70 mm2 used per vehicle on average. Automotive usage is the largest sector, followed by industrial, and â€śotherâ€ť:
The auto sector has been expanding steadily for the last decade, due to the increasing use of automotive transceivers (CAN/LIN/FlexRay, over 50% in SOI), and class-D amplifiers in infotainment systems. On the industrial front, the driving products have been AC/DC converters, motor drivers, and Power over Ethernet.
The higher voltages and harsh environment have a lot to do with SOI migrating into these spaces â€“ junction temperatures can get up to 225Â°C, and the dielectric isolation of the buried oxide helps with high-voltage operation, electrostatic discharge (ESD), and electromagnetic interference (EMI) protection. And of course it is inherently radiation-hard for particulate radiation such as alpha-particles or neutrons, great for space and military applications.
In terms of the design considerations, the use of SOI eliminates parasitic latch-up, and the ability to use oxide isolation between circuit elements saves space when compared with diffused isolation in BCDMOS (bipolar-CMOS-DMOS) processes.
This can give a die size reduction of 40 â€“ 50%, depending on the design, so well worth considering even with a higher-priced start wafer.
Photonics SOI uses a different benefit of the buried oxide layer â€“ the ability to confine photons within a silicon waveguide. In yet more of those fortunate properties of silicon, it transmits infra-red light at 1.3 â€“ 1.6 Âµm, matching the wavelengths used in fibre-optic cables; and there is a large refractive index (RI) contrast between Si (n~3.5) & SiO2 (n~1.5), giving good total internal reflection to silicon waveguides on oxide.
The higher refractive index also means that the wavelength is shorter in silicon, so we can have much tighter turning radii than in oxide, allowing sharp bends in photonics chips. Add to that the capability of tuning the RI by tuning the doping, and manipulating the light by applying a voltage and injecting carriers to adjust the phase, and we can do photonic processing as well as the usual digital and analog electronic processing.
The main application at present seems to be photonic transceivers, both inside and outside systems, but there is plenty of R&D looking to take advantage of the potential, particularly as data rates move towards 100 Gb/sec.
Currently total production is only about 10,000 wafers/year, but being targeted mainly on interconnect inside and outside data centres, that is a low volume, high value part of the business. Looking to the future, Soitec expects that the growth in data as 5G arrives will push the need for photonics products, and Tom speculated that the high data rates required for 4K/8K virtual reality systems may also drive a consumer need for optical links to the headsets.
Almost four years ago Chipworks analyzed a Luxtera chip from a Molex active fibre optic cable, fabricated by Freescale (at the time, now NXP) in a 130-nm CMOS/photonic SOI process. Hereâ€™s an optical plan-view image of a pair of waveguides turning 90o:
Wide multi-mode waveguides come in from the left, narrow down and become single-mode waveguides before they turn 90o with a radius of 30 Âµm and exit at the top of the image.
Here we show a TEM cross-section of the narrow part of the waveguide:
The deep STI through to the buried oxide isolates the waveguide structure, and the shallow STI in the structure confines the optical signal to the central mesa. The extra width and the outer ribs likely act toÂ give mechanical stability and even out the stress in the central mesa, and there is a silicon nitride layer over the waveguide which acts as a silicide mask. They are in general uniformly doped, but when they become part of a Mach-Zender interferometer (MZI), a P-N diode is formed in the waveguide in order to modulate the phase of the optical signal by varying the reverse bias on the diode. Below are junction-stained SEM and scanning capacitance microscopy (SCM) cross-sections of one waveguide in a MZI. In the SEM image,Â the copper metallization has been etched out, but we can see the pairs of contacts to the SOI to bias the diode.
Germanium photodetectors are formed selectively on the SOI for receive and signal-monitoring functions, and a laser diode module is mounted on the die for transmit capability.
It is obvious from this example that SOI is an almost ideal material for part of the integrated photonics systems that we will need in the not-too-distant future. Unfortunately silicon is not good for generating light, and we still need the interface to cable, so photonics chips will have to be part of an integrated assembly.
Intel made it clear last year at their Data Center Day that they consider silicon photonics a key part of their â€śData Center Connectivity Landscapeâ€ť, from within-rack connection to across the data center itself, which can involve kilometers of interconnects:
They also see ~50% growth in the market in the next few years:
And it is clear from the new roadmaps (Photonic Systems Manufacturing Roadmap, and Heterogeneous Integration Technology Roadmap for Semiconductors) that technology and cost pressures are driving developments both in volume wafer manufacturing and wafer level assembly, as well as other areas such as optical through-silicon vias.
So, if we look at all the above applications, and include the predictions for FD-SOI, Soitec not only has bounced back from its travails of a few years ago, but as the main player in the SOI wafer business, it seems to have a solid future coming up.
- Soitec white paper â€śInnovative RF-SOI Wafers for Wireless Applicationsâ€ť
I should have posted this after IDF! Now we have Intel shipping photonic transceivers, likely with hybrid InP/Si lasers on board.
$5.1B seems a bit ambitious!