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The ConFab Preview

The agenda is set for The ConFab, to be held May 14-17, 2017 in San Diego at the iconic Hotel del Coronado. While reviewing the abstracts for just the Monday morning session, it struck me how well our speakers will cover the complex opportunities and challenges facing the semiconductor industry.

In the opening keynote, for example, Hans Stork, Senior Vice President and Chief Technical Officer, ON Semiconductor we will discuss the challenge to realize high signal to noise ratio in small (read inexpensive) and efficient form factors, using examples of image sensors and power conversion in automotive applications. “It seems that at last, after many decades of exponential progress in logic and memory technologies, the “real world” devices of power handling and sensor functions are jointly enabling another wave of electronics progress in autonomously operating and interacting Things,” he said.

Next, Subramani Kengeri, Vice President of CMOS Platforms Business Unit, GLOBALFOUNDRIES, will describe how the rapid growth of applications in the consumer, auto and mobile space coupled with the emergence of the Internet of Things (IoT) is driving the need for differentiated design and technology solutions. “While die-cost scaling is slowing down and power density is emerging as a major challenge, fabless semiconductor companies are hungry for innovation using application optimized technology solutions. Specifically, emerging SoC innovations are driving the need for low-power, performance, cost, and time-to-volume that solves the issues of voltage scaling and integration of “user-experience” functions,” he notes.

Islam Salama, a Director with Intel Corporation responsible for packaging substrate Pathfinding of the high-density interconnect across all Intel products, looks at it from a connectivity perspective. “The pervasive nature of computing drives a need for connecting billions of people and tens of billions of devices/things via cloud computing. Such connectivity effect will generate tremendous amounts of data and would require a revolutionary change in the technology infrastructures being used to transmit, store and analyze data,” he said.

Next-generation electronics will require several new packaging solutions, he adds. Smaller form factors, lower power consumption, flexible designs, increased memory performance, and-more than ever, a closely managed silicon package, co-optimization and architectural innovations. Heterogeneous integration through package with technologies such as system in package (SIP), on package integration (OPI) and fan-out (WLFO and PLFO) are poised to change the packaging industry and play a disruptive role in enabling next generation devices.

Heterogeneous Integration is also the focus of a talk by Bill Bottoms, Chairman and CEO, Third Millennium Test Solutions. Bill will report on the collaboration in the making of the HIR Roadmap to address disruptive changes in the global IT network, the explosive growth coming for IoT sensors and the multi-sensor fusion and data analytics that extract “awareness” from the expanding data.

I’m very much looking forward to these and many other talks this year, and the exciting panel discussions and networking events we have planned.

10 Reasons to Attend The ConFab this June

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The ConFab Conference and Networking Event will be held June 12-15. Presented by Solid State Technology, this executive-level event is designed exclusively for those driving growth and innovation in the semiconductor industry. With a theme the “New Age of Innovation for Semiconductors,” it features deep insights on the challenges and opportunities facing the industry and also offers powerful networking opportunities. Here are my top 10 reasons to register now.

The keynotes. Hear from Dr. Thomas Caulfield, senior vice president and general manager of the GlobalFoundries’ latest leading-edge 300mm semiconductor wafer manufacturing facility; Sunny Hui, senior vice president of worldwide marketing, Semiconductor Manufacturing International Corp., and Bill McClean, President of IC Insights.
Dynamic networking. A big part of The ConFab is the networking. There are plenty of opportunities to get together at breakfast, lunch and for evening receptions. The semiconductor industry has undergone unprecedented consolidation over the last year and the only way to know who’s who in the new landscape it to get out and talk to people.
Strategic business meetings. We arrange strategic meetings between technology suppliers and manufacturers, including IDMs, foundries and OSATs. Fabless companies, which are increasingly driving manufacturing decisions, are also involved.
The big picture. You’ll walk away with a high level overview of the myriad of challenges and opportunities now facing the semiconductor industry. In our first session, speakers will include Dan Armbrust, CEO and co-founder, Silicon Catalyst; Lode Lauwers, VP, Business Development, imec; Kevin Gibb, Editor for the Research Division at TechInsights; Hughes Metras, VP Strategic Partnerships N.A., CEA Leti; and Mark Reynolds, Senior Director Industry Development, New York Empire State Development.
Why new thinking is required for IoT innovation. The semiconductor industry needs to change the way it thinks about innovation, both technical innovation and business model innovation, especially when it comes to the Internet of Things (IoT). A panel session of experts and visionaries will discuss IoT’s role in various applications, how it will require investments in gateways, networks, servers and data analysis computers, and why IoT is the new big driver for semiconductor technology. Panelists include Uday Tennety, Director, Strategic Engagements and Innovation, GE Digital; Rajeev Rajan, Vice President of Product for Internet of Things, GlobalFoundries; Kelvin Low, Foundry Marketing, Samsung SSI; and Tim Hewitt, Director of Industry Solutions at Siemens. Come and ask questions!
Fab Management. Today’s fab managers face a long list of everyday concerns and long term challenges. They must continually be thinking of ways to improve operational efficiency, optimize asset utilization, boost tool and worker productivity (and safety), increase throughput, maximize yield and reduce defectivity. A session will focus on this issues, with a focus on real, hands-on solutions. Speakers will include: Sanchali Bhattacharjee, Technology Strategist: Component Supply Chain, Intel; Ardy Sidwha, Sr. Director, Innovation & Technology (R&D) at QuantumClean; Rick Glasmann, Senior Director and Managing Director FE Operations Temecula; and Mike Czerniak, product marketing manager at Edwards.
System Level Integration: New Directions in Packaging. System level package innovation and heterogeneous integration encompass a wide range of technologies, including module and 3D packaging, system-in-package (SiP), fanout, and embedded technologies. But questions remain. How will these technologies be utilized in advanced data centers & network systems, in future smart phones, and the growing medical, industrial and lifestyle IoT applications? A session, sponsored and organized by IEEE’s CPMT Society, will look at how packaging technologies are enabling innovative solutions that achieve system application requirements while maximizing system level performance, and, meeting cost, performance, form factor and reliability goals.
China. With the “Made in China 2025” initiative, China is aiming to improve the self-sufficiency rate for ICs in the nation to 40% in 2020, and boost the rate further to 70% in 2025. What will be key is how Chinese companies can gain access to 16/14nm, 10nm, and 7nm technologies as well as DRAM and 3D NAND technologies. China is also planning to be global leader in 5G, with test development in 2018 and initial broadband deployment in 2020. This session will examine how the China “wild card” and increased M&A activity designed to bring advanced technology into China is a true game-changer for the worldwide semiconductor industry. Following SMIC’s Sunny Hui’s keynote, presenters will include Ed Pausa from PricewaterhouseCoopers and Jimmy Goodrich, Vice President, Global Policy, Semiconductor Industry Association. Bill McClean will also discuss China in his talk.
Great location. The ConFab will take place at the beautiful Encore at The Wynn right in downtown Las Vegas.
Collaboration. It’s clear that the need for real collaboration has never been greater. At The ConFab, industry leaders will gather to tackle tough questions, take a look at the new post-consolidation landscape, network in a unique environment and collaborate on the future.

Register now by contacting Sally Bixby at [email protected]. Complimentary passes are available to qualified VIPs. You can also check out The ConFab website. I hope to see you there!

IoT and The ConFab 2015

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I’m delighted to announce the keynotes and other key speakers for The ConFab 2015, to be held May 19-22 at The Encore at The Wynn in Las Vegas.

Our first keynote, on Wednesday, will be Ali Sebt, President and CEO of Renesas America, who will provide his insight on monetizing the Internet of Things. He’ll discuss how intelligent and connected platforms will enable new value chains based on a platform play, or an associated ecosystem play.

Our second keynote, on Thursday, will be Paolo Gargini, Chairman of the ITRS. The newly “re-framed” ITRS roadmap process has been extended with studies of key requirements from a system-level perspective that includes heterogeneous integration, new revolutionary devices and new ways of physical and wireless connectivity. Paolo will describe what is known as the ITRS 2.0.

Also slated to speak is Subramani Kengeri, Vice President, Global Design Solutions at GLOBALFOUNDRIES, who will talk about how the design eco-system is a critical enabler for semiconductor growth. Subi says that the rapid evolution of applications in the consumer and mobile space coupled with the emergence of the IoT are driving innovations that push the limits of power, performance, cost, and time-to-volume. At the same time, next generation SoCs are demanding stronger design and technology co-optimization solutions—some of which are optimal in main-stream technologies—to support complex design integration functions.

Lode Lauwers, Vice President Business Development, at imec will continue the IoT theme, focusing on how it is driving technology trends on system scaling and semiconductor manufacturing effectiveness. Lode says to realize the promises of an augmented, connected sustainable world, promised by the IoT, the IC industry faces significant challenges both at a distributed level, with the development of ultralow power sensor and radio technologies, as well as in the cloud, with huge computational requirements to store and process data.

Jim Feldhan, president of Semico, will present the outlook for key components of the IoT market. Wearables, electronic health care, smart home, cities and cars all promise to be high volume semiconductor markets. What will these markets look like? What are some the enabling technologies necessary to make IoT a reality? Come to The ConFab 2015 and find out! See www.theconfab.com for more info.

Can we take cost out of technology scaling?

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There is much talk these days about continued scaling, including some recent posts by my colleague Ed Korczynski, in “Moore’s Law is Dead” Part 1 (What?) and Part 2 (When?). At The ConFab in June, keynote speaker, Dr. Gary Patton, vice president, semiconductor research and development center at IBM, talked about scaling, adding some historical perspective. I previously blogged about the “three fundamental shifts” that Patton believes will lead to a bright future for the semiconductor industry.

“We will keep scaling,” he said. “We have shown a tremendous ability to innovate and keep moving that technology forward.”

In the 1990s, Patton notes that life was actually pretty simple. “You brought in a new lithography tool, you scaled the horizontal dimensions, you scaled the vertical dimensions and you got a new technology out. It was better performance, the same power density, and you could do a lot more on the chip,” he said.

Around 2000, we hit the gate oxide limit. “Gate oxide got to be abount three atomic layers. We could have said at that point ‘game over, scaling has ended.’ But guess what, we innovated. We came up with a pretty fundamental shift in ideas which is let’s change the fundamental properties of silicon. If we can strain the silicon, we can enhance the mobility. We can change the gate oxide. We can enhance the coupling between the gate and the channel. And that’s what we get over that last decade. We said let’s go from SRAM to a very high performance eDRAM (embedded DRAM) so we can put a lot more memory next to the processor because we knew memory was a key gating factor for the processor speed. This enabled the personal computing era and smart consumer electronics,” Patton said.

In 2010, we were at another one of these inflection points. “It’s not surprising that the improvements in 20nm are less than people would like because we really reached the end of the planar device era. Again, we were saying ‘game over, we’re done scaling.’ But no, we continue to innovate. The next decade is really about 3D. 3D devices, finFETs, or 3D chip integration,” he added.

Patton said that design technology co-optimization will be a key piece of getting through the next decade. “That will probably take us to about 2020,” he said. At that point we’re going to “hit the atomic dimension limit and we’re going to have to do it all over again. Here, we’re going to get into nanotechnology. Nanowire devices, silicon nanowires, carbon nanotubes, photonics and multi-chip stacking to bring things together. That will enable wearable computing, everywhere connectivity and cognitive computing.”

Patton said the problem is not physics. “We’re going to have solved the physics problems,” he said. “The problem is financial.” Patton showed a chart (below) that depicted the history of our industry from 1980 to present. “What drove the industry was smaller features, which enabled better performance and better cost per function. It enabled new types of applications, and that enabled larger markets. If you look in this time period, there’s about a six order of magnitude improvement in cost per transistor and that enabled a seven order of magnitude increase in consumption of silicon transistors,” he said.

The challenge we’re facing right now is depicted below, showing the compound growth rate reduction and the cost of a circuit. On the x-axis is linear scaling. “We’ve typically targeted about a 0.7X linear scaling, which means from an area perspective, you get about 50% improvement. Note the line, 50%, doesn’t go through 50% improvement because with each new technology, there is some increase in complexity. It might be more like 30% improvement at the die level. If we’re really good and provide some enhancements in the technology, self-aligned processes, things like that, we may get it to 40%. So 30-40% is about the range we’ve been getting in terms of the cost per die improvement as we scale up.

“The challenge we’re facing now is two fold. Number one, we’re struggling to get that 0.7X linear scaling. It might be about 0.8X. And we’re adding a lot more complexity, especially when you adding double and triple patterning .The focus today in innovation has got to be heavily focused on ‘how do we drive cost?’ Not just how do you scale, because scaling would add a lot of extra cost at this point. How do we drive cost down, how do we keep adding value to the technology. The model is changing. Moore’s Law can still hold, but we have to focus on the cost equation. So there’s really two parts. Technology innovation which is focusing on the patterning, focusing on the materials, the processing, and how do we drive that to take cost out of the technology scaling,” Patton said.

Three fundamental shifts

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At The ConFab last week, Dr. Gary Patton, vice president, semiconductor research and development center at IBM, said there is a bright future in microelectronics (I heartily agree). He said that although there seems to be a fair amount of doom and gloom that scaling is ending and Moore’s Law is over, he is very positive. “There are three huge fundamental shifts that are going to drive our industry forward, will drive revenue growth and will force us to keep innovating to enable new opportunities,” he said.

The first fundamental shift is the explosion of applications in the consumer and mobile space. Patton noted examples such as cars that can drive themselves and can detect people and bicyclists and avoid them, smart phones for as little as $25, wearable devices that not only tell you what you’re doing but how you’re doing, and 4K television. “That is an incredible TV system, but it’s going to demand a lot of bandwidth; twice the bandwidth that’s out there today. If you turn on your 4K system, your neighbors are going to start to notice it when they try to access the internet,” he said.

Patton said that it’s estimated that today there are about 12.5 billion devices connected to the internet. That’s expected to grow to $30 billion by 2020. This represents the second fundamental shift commonly known as Big Data. “All these interconnected devices are shoving tremendous amount of data up into the cloud at the rate of 1.5 Exabytes (10¹⁸) bytes of data per month,” Patton said. “And that’s grown by about an order of magnitude in just the last 13 years. The estimate is that in the next 4 years, it’s going to go up another order of magnitude. It’s accelerating.”

The third fundamental shift is with all this data going up into the cloud, the data is almost all unstructured data, such as video and audio. “It’s related data but disconnected. How do we take that data and do something with it? That brings us to analytics and cognitive computing. We have really just started in this arena.”

So there you have it. Three reasons to be very positive about the future of the semiconductor industry: an explosion of applications, the rise of big data and the need to analyze all that data.

GLOBALFOUNDRIES’ Kengeri to speak at The ConFab

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Subramani Kengeri, Vice President, Advanced Technology Architecture at GLOBALFOUNDRIES will speak at The ConFab 2014 on the “techno-economics” of how the relatively small semiconductor industry ($350 billion or $0.35 trillion) is driving the $85 trillion gross world product (GWP). He notes that semiconductors are only a fraction of GWP, but a critical enabler of global economic growth and productivity. Cost effective technology innovations have kept Moore’s law alive, although techno-economic challenges are mounting on each successive node. The cost of building a new advanced fab has reached $6B. Process development and chip design costs are going up astronomically, while next generation SoCs in the IoT era are pushing cost-per-function to unprecedented levels, he says. His talk will review advanced design and silicon technology challenges posing threats to cost effective scaling, potentially impacting global GWP and productivity.

Subramani (“Subi”) is responsible for defining competitive process architecture on advanced nodes in support of “first time right” technology development. He is responsible for determining the technology feasibility, competitiveness and manufacturability of all elements of technology platform and to establish the advanced technology roadmap for GLOBALFOUNDRIES.

Subramani joined GLOBALFOUNDRIES in 2009 as the Vice President of Design Solutions. He implemented strategic Design enablement initiatives and established a strong foundation for collaboration with Design eco-system, before moving to focus on R&D. He started his Semiconductor career at Texas Instruments and prior to joining GLOBALFOUNDRIES, he was the Senior Director of Design and Technology Platform at TSMC.

Extreme Stress for Existing Foundry/Fabless Model

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Dr. Roawen Chen, senior vice president of global operations at Qualcomm, will provide the keynote talk at The ConFab 2014 this year. The event will be held June 22-25 at The Encore at The Wynn in Las Vegas.

In his talk, Dr. Chen, will describe how the increased performance and the rapid shift from traditional handsets to consumer computing device post a number of manufacturing and supply chain challenges for fabless chip makers. He says the scale of the challenges also creates an “extreme stress” for the existing foundry/fabless model to defend its excellence in this dynamic landscape. In this talk of “what’s on our mind?” he will deliberate on a number of headwinds and opportunities.

In his role at Qualcomm, Roawen oversees the worldwide operations and supply chain, silicon and package technology, quality/reliability, and procurement functions for the Qualcomm semiconductor business. He has overall responsibility for driving the global integrated fabless strategy and execution.

Roawen is an experienced leader in all aspects of semiconductor operations and supply chain management with a solid background in leading large-scale fabless operations. In addition to his strong technical depth, he has proven experience in building close supplier and vendor relationships and executing to support customer demand and product development. Prior to Qualcomm, Roawen was Vice President of Manufacturing Operations at Marvell Semiconductor in Santa Clara, California. During his more than 12 years at Marvell, Roawen held a variety of leadership roles, including Vice President and General Manager of the Communications and Computing business unit and Vice President and General Manager of the Connectivity business unit. He has also served in management roles in Marvell’s Foundry Operations and Manufacturing Technology groups.

Prior to Marvell, Roawen held technical positions at TSMC-USA and Intel. He earned a bachelor’s degree in Physics from National Tsing-Hua University in Taiwan, a master’s degree in Materials Science from the University of California, San Diego and a PhD in Electrical Engineering and Computer Science from the University of California, Berkeley.

At The ConFab 2014: The Outlook for the Semiconductor Industry

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The semiconductor market will continue at a steady growth rate for the next several years. For a semiconductor company to achieve significant growth in this ultra-competitive environment, it needs to identify market opportunities and predict the future, in terms of markets, both regionally and globally, anticipate technological advancements, as well as envision new applications. At The ConFab in June, Session 1 will provide an overview of these critical issues.

The presenters will be:

Vijay Ullal, COO, Fairchild Semiconductor

Dave Anderson, President and CEO, Novati Technologies

Gopal Rao, Senior Director Business Development, SEMATECH

Adrian Maynes, Program Manager, F450C

Bill McClean, President, IC Insights

Here’s an overview of what each presenter plans to cover:

The Economics of Semiconductor Manufacturing and the Escalating Cost of R&D

Vijay Ullal, COO, Fairchild Semiconductor

While innovation in semiconductor technology is driving change in industries from automotive to mobile, and the sophistication of computers, mobile devices, automobiles, industrial systems and consumer goods evolves, greater pressure is placed on semiconductor research and development (R&D) as well as Supply Chain Management (SCM). Now, the bar has been raised from not only delivering leading-edge technology, but also to delivering far greater value to an organization. This presentation will use examples of to focus R&D as well as revitalize your supply chain in order to highlight your competitive advantages, and better meet these market place demands by moving beyond the “product sell” to an approach that focuses instead on the key attributes customer’s value.

More-than-Moore: A New Era of Innovation

Dave Anderson, CEO, Novati Technologies

The semiconductor industry has focused on Moore’s Law for more than 40 years in its quest for ever shrinking geometries to squeeze more transistors on a chip and improve device speed and performance. Digital microcircuits have benefited immensely from this extreme scaling but, with fewer companies having the ability to support further scaling, More-than-Moore (MtM) has emerged to apply decades of semiconductor process knowledge to novel applications to produce state-of-the-art biochips, sensors, actuators, imagers and more. Perhaps most importantly, MtM technology is enabling companies to build these components more cost-effectively and with better performance and smaller size than ever before.

Providing a significant advantage over traditional volume foundries, a new wave of boutique nanotechnology development centers is in a unique position to integrate new materials with custom processes. This provides a rapid acceleration of development and production for world-leading ideas and breakthrough MtM products.

The result is a new era of innovation that couples the best of the past with future demands to create valuable applications and markets. The era for enabling the most rapid, but affordable, new product development and deployment has begun.

Enabling the Supply Chain to Accelerate R&D

Gopal Rao, Senior Director of Business Development, SEMATECH

There is a push/pull market energy that is now, more than ever, influencing the device makers, suppliers and the consumers who are thirsty for innovative mobile computing and connected devices. The IC industry has relied on a push based roadmaps to bring products to market. It is important that we acknowledge that the consumer appetite for innovative and cool products has created a pull system that may be considered a roadmap. The challenge facing the whole IC industry is how to recognize, rationalize and leverage these push/pull roadmaps. This talk examines this IC industry challenge and opportunity, specifically in moving the vast supply chain to feed into this fast moving market. The pace of R&D through entire supply chain is essential in staying ahead of the curve and driving down cost of technology and manufacturing. Radical, innovative product designs to meet consumer demand will push into the IC supply chain the need to identify and develop significant cost/performance improvements in IC device performance. What are these improvements? Are the current roadmaps highlighting them or do we need to better, integrated intelligent roadmap that helps the supply chain stay on treadmill of innovation and cost reduction?

450mm Transition towards Sustainability: Facility & Infrastructure Requirements

Adrian Maynes, F450C Program Manager

It is widely accepted that in the next few years the semiconductor industry will begin to transition to the next generation 450mm wafer size. Experts throughout the semiconductor industry are striving to make 450mm a reality from a technical and manufacturing standpoint. Along with the increase in wafer size, the industry is closely examining impacts to the facility infrastructure, as merely scaling the manufacturing process is not a practical option. The size of the 450mm facility infrastructure and its associated utility consumption projections would simply exceed affordability and resource availability.

The facility experts involved in establishing and later implementing 450mm infrastructure requirements are facing the same degree of challenges as the IC and equipment manufacturers. For the first time in semiconductor history, facility professionals are collaborating closely with the industry’s top five consolidated IC manufacturers to bring their collective expertise to bear on the most pressing 450mm fab issues. With special focus on safety, cost, schedule, sustainability, and environmental footprint, this global consortium of industry specialists is aiming to reduce the cost of production, increase productivity for manufacturers, and reduce the environmental footprint on a per chip basis

This presentation will address these various infrastructure requirements and potential issues for a more sustainable manufacturing process. The session will be co-presented by leaders of the Facilities 450mm Consortium (F450C) and the Global 450mm Consortium (G450C). These two groups are collaborating as experts from across the entire supply chain to ensure a smooth transition to the 450mm technology.

Major Trends Impacting the IC Industry of the Future

Bill McClean, Presdient, IC Insights

IC Insights forecasts that 2014 will continue the integrated circuit industry cyclical upturn that began in 2013. This cyclical upturn is expected to gain momentum over the next several years, resulting in a 6.4% IC market CAGR over the 2013-2018 time period, which would be more than 3x the 1.7% CAGR the IC market displayed from 2007-2012. Although a high level of uncertainty still looms over the global economy, sales of smartphones and tablet PCs continue to soar. IC Insights will present its forecast for the IC market in the context of the IC industry cycle model. In order to make sense out of the current turmoil, a top-down analysis of the IC market will be given and include trends in worldwide GDP growth, electronic system sales, and semiconductor industry capital spending and capacity.

Normal
0

false
false
false

EN-US
X-NONE
X-NONE

/* Style Definitions */
table.MsoNormalTable
{mso-style-name:”Table Normal”;
mso-tstyle-rowband-size:0;
mso-tstyle-colband-size:0;
mso-style-noshow:yes;
mso-style-priority:99;
mso-style-parent:””;
mso-padding-alt:0in 5.4pt 0in 5.4pt;
mso-para-margin-top:0in;
mso-para-margin-right:0in;
mso-para-margin-bottom:8.0pt;
mso-para-margin-left:0in;
line-height:107%;
mso-pagination:widow-orphan;
font-size:11.0pt;
font-family:”Calibri”,”sans-serif”;
mso-ascii-font-family:Calibri;
mso-ascii-theme-font:minor-latin;
mso-hansi-font-family:Calibri;
mso-hansi-theme-font:minor-latin;}

The ConFab R&D Panel is Set

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A panel session at The ConFab, to be held June 22-25 in Las Vegas, will focus on how the semiconductor industry can continue to innovate in an environment where lower revenue growth is combined with rising development costs and consolidation. The panel will discuss where the next big growth drivers will come from and the ability of the industry to continue scaling and remain on Moore’s Law through the introduction of new technologies such as EUV, Advanced Packaging and 450mm. How will the costs to develop these and other technologies affect innovation and what levers can be utilized to gain more efficiencies in R&D. The panel will also discuss what role startups will play in the industries going forward and how can increased collaboration benefit the industry.

The panel, to be moderated by Scott Jones of Alix Partners, will consist of:

Rory McInerny, Vice President Platform Engineering Group, Intel

Chris Danely, Senior Analyst, JP Morgan

Mike Noonen, Co-founder, Silicon Catalyst

Lode Lauwers, Senior Director of Business Development, imec

Some of the subjects that will be covered:

Where does do the next growth drivers come from?

When will wearables, medical devices and the internet of things really drive revenue growth?

What challenges do we have on the R&D side in servicing the growth areas more quickly?

How are the costs of scaling and the development costs of SOCs affecting growth?

What advances from the chip design and architecture side are compensating for the challenges in scaling?

What view does the institutional investing community have on investing in innovation versus acquiring it?

What is the state of the Start-up environment in Semiconductors?

How do we leverage collaboration more to improve on our return on R&D investment?

Click here for more information on The ConFab 2014 agenda.

Qualcomm’s Dr. Roawen Chen to keynote at The ConFab

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I’m delighted to report that Dr. Roawen Chen, Senior Vice Present of global operations at Qualcomm, has accepted our invitation to deliver the keynote talk at The ConFab, on Monday June 23^rd. As previously announced, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York, will deliver the keynote on the second day, on Tuesday June 24^th. I’m thrilled to have these two visionaries speak to The ConFab audience.

The ConFab will be held June 22-25 at The Encore at The Wynn in Las Vegas.