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3D Packaging Processes

Mon, 3 Mar 2008
adapted for print by AP editors

(March 5, 2008) — This article is the third in a series on 3D packaging technology, and summarizes information presented during a January 2008 webcast hosted by Advanced Packaging magazine. Participants were: Fred Roozeboom, Research Fellow, NXP Semiconductors and professor at TU Eindhoven; Kai Zoschke, Research Engineer for Fraunhofer IZM; and Thorsten Matthias, Director of Technology North America, EV Group.

System-in-Cube Technology Addresses Parasitics, KGD

Tue, 3 Mar 2007
(March 7, 2007) COSTA MESA, CA — Irvine Sensors Corporation demonstrated its 3D packaging technologies to stack four 500-mHz DDR memory chips without operating-speed degradation, which was verified by the chip maker. The company will now explore commercial exploitation of packaging techniques for the memory chips.

Samsung Develops DRAM Stack with TSVs

Mon, 4 Apr 2007
(April 23, 2007) SEOUL, South Korea — Samsung Electronics Co., Ltd., has developed an all-DRAM stacked-memory package using through-silicon vias (TSVs) housed in aluminum pads to avoid performance slow-downs caused by the redistribution layer. The company applied a proprietary wafer-thinning technique to eliminate warped die in the low-profile package.

IEEE Recognizes Fraunhofer's Reichl

Wed, 4 Apr 2007
(April 18, 2007) BERLIN — The IEEE components, packaging, and manufacturing technology (CPMT) society — an international forum for scientists and engineers in microsystems packaging design and manufacture R&D and development — named professor Herbert Reichl, director of Fraunhofer IZM, recipient of its electronics manufacturing technology award.

Consumers, Integration Dictate Future of MEMS, 3-D Packages

Wed, 1 Jan 2007
(January 24, 2007) LYON, France and PITTSBURGH — The future of MEMS and 3-D packages relies on similar factors — consumer drivers and increased integration — according to industry analysts. 3-D integration will affect MEMS and IC packaging industries, says Yole Développement's "3-D ICs." Advanced packages require acceptance from the consumer market to reach targets for technological advancement, commercialization, and sector revenues.

Thin-wafer Handling System

Tue, 7 Jul 2007
A polymeric spin-on coating, WaferBOND HT-250, temporarily attaches device substrates to a carrier substrate, enabling wafer thinning and subsequent processing. It will reportedly permit advanced packaging processes such as the creation of through-silicon vias (TSVs), 3D stacking, and other etching, plating, and follow-on processes.

CEA Installs Alcatel Systems for TSVs

Mon, 7 Jul 2007
(July 23, 2007) GRENOBLE and ANNECY, France — Alcatel Micro Machining Systems will provide two 200-mm DRIE and LTPE CVD systems at CEO/Léti-Minatec R&D institute under a joint development agreement. The parties will collaborate to develop and demonstrate a suite of turnkey silicon microvia technologies for 3D integration at wafer and die levels.

Seminar Series Targets Integrated Process Solutions for 3D Packaging

Tue, 9 Sep 2007
(September 25, 2007) MUNICH, Germany— SUSS Microtec, NEXX Systems, and Surface Technology Systems (STS), manufacturers of semiconductor process equipment, announced their collaboration with Fraunhofer IZM to demonstrate integrated process solutions for 3D wafer-level packaging (WLP).

Embedded Passives' Role in 3D Packaging

Mon, 10 Oct 2007
By Happy Holden, Mentor Graphics, Inc.
3D packaging technology is evolving rapidly to improve functionality and performance while maintaining a compact form-factor. Embedded passive components (EP) will play a major role in all of these 3D schemes.

Invensas, Allvia ink 3D IC tie-up

Tue, 11 Nov 2011

Invensas has "acquired" dozens of 3D IC packaging patents from Allvia, and the two have agreed to further collaboration in the area.

3D packaging enters the mainstream: Attend the conference

Tue, 11 Nov 2011

2.5D, 3D and Beyond - Bringing 3D Integration to the Packaging Mainstream will take place November 9 in Santa Clara, CA. The MEPTEC conference follows the trend of 3D and 2.5D packaging moving from roadmap to factory production.

Xilinx FPGA boasts 6.8B transistors

Tue, 10 Oct 2011

Xilinx Inc. (Nasdaq:XLNX) began shipping its Virtex-7 2000T field programmable gate array (FPGA), a programmable logic device with 6.8 billion transistors: 2 million logic cells, a die-stack architecture, low power consumption, and a more flexible design than large ASICS and monolithic FPGAs.

TSV electroplating dev team unites SVTC, Amerimade Technology, Shanghai Sinyang Semiconductor Materials

Wed, 10 Oct 2011

Nanotech accelerator SVTC Technologies, wet chem equipment maker Amerimade Technology, and chemicals company Shanghai Sinyang Semiconductor Materials will collaborate on electroplating processes for TSV that are production-ready for advanced packages and MEMS.

SUSS MicroTec wins thin-wafer temporary bonder order

Tue, 10 Oct 2011

SUSS MicroTec, in partnership with temporary bonding adhesive maker TMAT, will deliver SUSS MicroTec's new-generation high-volume temporary wafer bond tool clusters to a leading IDM.

Fraunhofer, EVG develop temporary wafer bonding for thicker die

Tue, 10 Oct 2011

EV Group (EVG) will work with Fraunhofer IZM's ASSID research center to develop temporary bonding/debonding technologies for thicker die structures, some as large as 600

Fraunhofer IZM's packaging center installs Altatech CVD

Tue, 10 Oct 2011

All Silicon System Integration Dresden (ASSID) installed an Altatech 300mm CVD tool for dielectric film deposition on advanced through silicon vias (TSV), with diameters as small as 10

Thin wafers win majority in electronics by 2016

Thu, 10 Oct 2011

Thanks to MEMS, 3D packaging, LEDs, power devices, and other applications, thinned wafers will be the majority of wafers in the market by 2016, according to Yole D

Rudolph wins TSV inspection systems order

Mon, 10 Oct 2011

Rudolph Technologies Inc. (NASDAQ:RTEC) shipped its Wafer Scanner 3880 3D Inspection System, multiple NSX Macro Defect Inspection Systems and its Discover Yield Management Software Suite to a leading semiconductor manufacturer for use in developing through silicon via (TSV) structures.

Samsung embedded memory fits 8 die in 1.4mm stack

Thu, 9 Sep 2011

Samsung Electronics Co. Ltd. developed a high-performance 64GB embedded memory with 64Gb NAND. The package contains an 8 die stack in a low profile for smartphones, tablets and other mobile devices.

IMAPS International 2008 In Review

Mon, 11 Nov 2008
By Gail Flower, Editor-in-Chief
This year's IMAPS International Symposium had great international participation, good attendance and excellent presentations from keynoters to the technologically cutting-edge educational papers. It was election day when the IMAPS conference began, and by the second day of the conference, a new president entered the picture. Therefore, the first day proceeded without a rush of attendees as expected, but the second perked up with lively conversation.

Dual-purpose 300mm dicing frame prober

Mon, 11 Nov 2008
The WDF 12DP is designed to address increased demand for probing ultrathin and diced wafers, and wafer-level testing of chip-scale and wafer-level packaging, stacked, and 3D technologies, as well as KGD testing of ultra-hin wafers, singulated wafers, and strips on a dicing frame.

Electronics Industry Association News

Mon, 7 Jul 2008
(July 14, 2008) — IMEC and Qualcomm collaborate on 3D packaging technologies; IPC meets internationally to discuss urgent trends; iNEMI releases recommendations for lead-free alloy alternatives.

STMicroelectronics to Manufacture TSV-based Image Sensors on EV Group 300-mm Tools

Tue, 7 Jul 2008
(July 8, 2008) ST FLORIAN, AUSTRIA — EV Group(EVG)announced the order and successful installation of its 300-mm bonding, alignment, and photoresist fully automatic processing tools at ST Microelectronics'(ST) 300-mm through-silicon-via (TSV) pilot line in Crolles, France. The company says the tools will be used in the manufacture of CMOS imaging sensors (CIS) Using TSV technology.

Mask Aligner for 3D Packaging

Tue, 7 Jul 2008
The second-generation SUSS MA300, from SUSS MicroTec is a highly automated mask aligner platform for 300-mm and 200-mm wafers. Specifically designed for 3D packaging, it features a dedicated alignment kit for creating 3D interconnects for applications like chip stacking and 3D image sensor packaging. It also targets wafer bumping and wafer level packaging (WLP) applications, but can be used for other technologies where geometries in the range of 5 and 100 µm must be exposed.

June Names in the News

Mon, 6 Jun 2008
(June 30, 2008) It was a month for names in the news as acquisitions and evolving business strategies inspired executive appointments and reorganization; industry organizations added members and directors, and books got published. Company announcements came in from JP Sercel Associates, TRUMPF, Dage Precision Industries, ECD, Jordan Valley, Rogers Corp., Formfactor, Unisem Group, Mentor Graphics, and Alchimer.

Photonic Interconnects Enable the Continuation of Moore's Law

Tue, 11 Nov 2008
By Fran

SEMICON Europe: Connecting Companies for 3D Interconnects

Fri, 10 Oct 2008
By Paul Collander, Poltronics, Inc. At the recent Advanced Packaging Conference at SEMICON Europe in Stuttgart, Germany, (October 7-9, 2008) Fran

IMEC Research Energetically Stacks Up

Tue, 10 Oct 2008
by Gail Flower, Editor-in-Chief, Advanced Packaging
IMEC remains on the forefront of research in many areas including nanotechnology, RF MEMS packaging, flip-chip, substrates, organic electronics, CMOS-based research, solar cells, and 3D stacked integrated circuits. In 3D stacked packages an area of predicted high-growth, IMEC has announced notable achievements.

Advanced Materials CVD and ALD Tool

Tue, 10 Oct 2008
The AltaCVD chemical vapor deposition (CVD) and atomic layer deposition (ALD) tool from Altatech combines a unique vaporizer technology, chamber design, and gas/liquid panel integration. The combination of a proprietary reactor design and precursor introduction path with a pulsed liquid injection and vaporization is said to enable nanoscale control of thickness, uniformity, composition, and stoichiometry in complex materials.

Online Interview: Ziptronix Joins Low-cost Quest for True 3D-IC

Tue, 10 Oct 2008
By Fran

X-Ray Inspection Identifies Flip Chip Detects

Tue, 9 Sep 2008
Using 2D and 3D X-ray techniques to find and confirm manufacturing defects in flip-chip devices
By Evstatin Krastev, Ph.D. Dage Precision Industries, a Nordson Company
While flip chip design eliminates excessive packaging, high-density flip chip devices place a greater burden upon device inspection. The combination of 2D x-ray and CT analysis offers powerful analytical capabilities need for the complete inspection of flip-chip devices and stacked packages.

SEMICON West Exhibitor 2008 Spotlight

Tue, 7 Jul 2008
by Fran

DNP Develops Slim Leadframe

Thu, 1 Jan 2009
(January 29, 2009) TOKYO — Dai Nippon Printing Co. Ltd. (DNP) developed a package leadframe to slim down the semiconductor package mounted on electronic devices. The leadframe enables known good die (KGD) semiconductor packaging with a thickness of 0.15 mm, using precision plating processes.

Replisaurus/S.E.T. to Collaborate with IMEC on 3D Integration

Tue, 1 Jan 2009
(January 13, 2009) SAINT JEOIRE, France — Smart Equipment Technology (S.E.T.), a wholly-owned subsidiary of Replisaurus Technologies, announced a collaboration with IMEC to develop die pick-and-place and bonding processes for 3D chip integration using S.E.T.'s flip chip bonder equipment. As part of the collaboration, S.E.T. will join IMEC's Industrial Affiliation Program (IIAP) on 3D integration.

3D Packaging Technologies Steal the Show at IMAPS

Tue, 4 Apr 2008
By Fran

Wafer Bonder for CMOS Image Sensors

Tue, 9 Sep 2008
In response to market needs for 300mm process equipment capabilities to demonstrate 3D processes, SUSS MicroTec has introduced The XBC300. The XBC300 is designed for 3D integration and 3D packaging with through silicon vias (TSVs) and is ideal for the CMOS image sensor (CIS) early adopter market.

Online Interview: Wilfried Bair, SUSS MicroTec, Talks 3D

Thu, 9 Sep 2008
(September 25, 2008) WATERBURY, VT — Things may appear to be slow right now in the semiconductor industry, but fab expanision due to the 300mm transition, the focus of resources on improving factory efficiency, and the expected adoption of through silicon vias (TSVs) bodes well for equipment manufactures in 2009. Wilfried Bair, VP business development and general manager, Bonder Division talked to AP about how SUSS MicroTec is getting ready for 300mm and 3D integration.

SMT Magazine Presents Packaging Panel at IPC Midwest

Wed, 9 Sep 2008
(September 24, 2008) SHAUMBURG, ILSMT editor-in-chief Gail Flower chaired a panel comprising equipment supplier, laboratory, EMS provider, and consultant voices at IPC Midwest in Schaumburg, Ill. David Geiger, Flextronics International; Jacques Coderre, Unovis Solutions; Vern Solberg, STI - Madison; and Gene Dunn, Panasonic Factory Solutions of America spoke about emerging packaging technologies.

3D Technology and Beyond: 3D All Silicon System Module

Tue, 9 Sep 2008
By Ritwik Chatterjee, Ph.D., and Rao R. Tummala, Ph.D, Packaging Research Center—Georgia Institute of Technology
There is a need for miniaturization at the IC, module, and system levels. There is stil research and development required to bring this hetero-integration technology to cost-effective implementation with required reliability and performance needs. In addition to the module level, we must focus on performance, form factor, cost, and reliability of the entire system.

EV Group and Brewer Science Establish Ultra-thin Wafer Bonding Lab

Wed, 1 Jan 2009
(January 7, 2009) ST. FLORIAN, Austria and ROLLA, MO— In response to a call for localized support and increased demand of 3D IC process development in Asia Pacific, EV Group (EVG) and Brewer Science, Inc. have set out to outfit an ultra-thin wafer bonding lab in Taiwan. To this end, the companies announced the installation of an EVG 500 series wafer-bonding system at Brewer Science's Taiwan applications lab in Hsinchu Science Park.

EVG, AMAT pair for 3D thin-wafer bonding

Fri, 7 Jul 2009
EV Group and Applied Materials say they will jointly develop wafer bonding processes for making through-silicon vias (TSV) in 3D IC packaging applications, working as members within the Semiconductor 3D Equipment and Materials Consortium (EMC-3D).

Stepping up to the 3D challenge

Wed, 7 Jul 2009
Soitec's president and CEO, André-Jacques Auberton-Hervé, discusses the three pillars of 3D integration at the wafer level, as well as bonding at room temperature. Also noted is Soitec's partnership with IBM, announced during SEMICON West.

SEMICON West: Jan Vardaman and Paul Siblerud Analysis

Fri, 7 Jul 2009
Paul Siblerud, SEMITOOL, discusses the role of the EMC-3D consortium in developing new packaging technologies, such as through silicon vias (TSV). Jan Vardaman, TechSearch International, examines the barriers, and breakthroughs, around 3D integration.

3D integration: A status report

Tue, 7 Jul 2009
3D IC technology, an alternative approach to wire-bonded chip stacking utilizing interconnets with through-silicon vias (TSVs) fabricated with front-end-like processes, is a hot topic at SEMICON West, and the focus of an on-line virtual forum hosted by public relations firm MCA.

SUSS, Thin Materials Cooperate on Temporary Bonding for 3D Packaging

Wed, 7 Jul 2009
(July 8, 2009) GARCHING and MUNICH, Germany — SUSS MicroTec and Thin Materials, a semiconductor process development company, are cooperating on a temporary bonding solution to be used for challenging thin wafer handling technologies required for emerging 3D integration and packaging technologies. With this cooperation SUSS MicroTec extends its solution portfolio for temporary bonding and thin wafer handling.

AMAT Joins EMC-3D Consortium

Tue, 2 Feb 2009
Applied Materials, Inc. has joined the international EMC-3D semiconductor equipment and materials consortium, which focuses on 3D chip stacking and MEMS integration.


Mon, 2 Feb 2009

GLOBALFOUNDRIES, Amkor co-develop semiconductor assembly and test methods

Mon, 8 Aug 2011

GLOBALFOUNDRIES entered into a strategic partnership with Amkor (NASDAQ:AMKR) to develop integrated semiconductor assembly and test processes for advanced silicon nodes. The aim is integrated fab-bump-probe-assembly-test steps that can be commercialized across multiple customers and end-market applications.

Package-on-package (PoP) track at SMTAI

Wed, 8 Aug 2011

The SMTA will host conference events with Amkor, Research in Motion, and TechLead Corporation on package-on-package (PoP) 3D stacking at SMTA International (SMTAI), October 16-20 in Fort Worth, TX.

Inside the Known Good Die conference

Wed, 8 Aug 2011

The annual Known Good Die (KGD) conference, taking place Nov. 10 in Santa Clara, CA, will address semiconductor die testing, assembly, manufacturing, and business challenges, with the tagline "KGD in an Era of Multi-Die Packaging and 3D Integration."

MEMS, 3D packaging major factors in iNEMI roadmap

Tue, 8 Aug 2011

The 2011 iNEMI Roadmap, published by the International Electronics Manufacturing Initiative (iNEMI), includes a new chapter on MEMS and sensors, and an expanded chapter on packaging to include substrates discussions.

SEMI convenes system-in-package summit alongside SEMICON Taiwan

Fri, 8 Aug 2011

SEMI will hold the first-ever SiP Global Summit, September 7-9, co-located with SEMICON Taiwan. Three forums cover system in package (SiP) test, the "3D IC era," and the requirements of mobile electronics.

Lack of EDA tools, thermal issues impeding 3D packaging technology

Wed, 8 Aug 2011

Amkor's Ron Huemoeller shares his thoughts about two panels from SEMICON West, on 2.5D silicon interposer packaging technologies and its supply chain, and 3D packaging technology and its ecosystem.

TI achieves volume production with stacked clip-bonded QFN

Thu, 7 Jul 2011

Texas Instruments has shipped more than 30 million units of its PowerStack packaging technology, a combination of chip stacking and clip bonding that is designed to improve performance and chip densities in power management devices.

TSV zen comes down to wafer processing balance

Tue, 7 Jul 2011

3D semiconductor packaging processes involve various groups, and standards are important in the hand-offs between them, explains Mark Berry, sales director at Metryx. He covers how to use metrology to protect wafer yields in 3D packaging.

3D IC with TSV show significant advances in last 12 months

Tue, 7 Jul 2011

Dr. Phil Garrou summarizes the significant commercial strides made over the past 12 months in 3D IC integration -- as defined vs. other "3D" technologies -- thanks to the promised combination of low cost and high performance.

Suss MicroTec 3D IC workshop addresses thin wafer handling and testing

Mon, 7 Jul 2011

At SEMICON West, 100+ attendees gathered at the Suss MicroTec workshop "3D Integration: Are we there yet?" to hear technical experts from around the globe to present updates on the status of 3D technology.

Optomec aerosol jet printing featured as wire bond, TSV alternative at IMAPS Device Packaging

Tue, 3 Mar 2011

Optomec Aerosol Jet product manager Mike O’Reilly will give a presentation titled "Aerosol Jet Printing as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications" at the IMAPS Device Packaging Conference on March 9.

Samsung announces wide I/O DRAM with TSVs for mobile apps

Sun, 2 Feb 2011

Weeks after announcing a 40nm 8GB DDR3 memory with 3D through-silicon vias (TSV), Samsung is showing a wide I/O 1GB DRAM also utilizing 3D TSVs, targeting mobile applications.

K&S high volume fine pitch Cu wire bonding

Wed, 2 Feb 2011

Figure. Copper transition and roadmap planning. SOURCE: Kulicke & SoffaAs gold becomes more expensive, copper wire bonding becomes more appealing for chip packaging. Reverse bonding, fine-pitch bonding, looping, second bonds, and other technologies are ramping on roadmaps, according to Kulicke & Soffa (K&S).

Advanced transmission lines replacement for TSVs

Fri, 2 Feb 2011

Jamal Izadian, co-founder & president of RFCONNEXT, makes the case for shaped membrane transmission lines (SMTL) for use in high-speed 3D packaging applications. SMTL supports and improves flip-chip, micro-bumping, wafer thinning, system-in-package (SiP), package-on-package (PoP), and other packaging processes by extending the bandwidth and high-speed limits of these technologies.

Semiconductor industry veteran takes helm at Minco Technology Labs

Fri, 1 Jan 2012

Minco Technology Labs, hi-rel semiconductor die processing, packaging and test provider, appointed board member Bill Bradford as president and CEO.

Samsung Electronics ramps embedded multi-chip packaging with memory products

Thu, 1 Jan 2012

Samsung Electronics began producing embedded multi-chip package (eMCP) memory for use in entry- to mid-level smartphones. The products use low power double-data-rate 2 (LPDDR2) 30nm DRAM and 20nm NAND flash memory.

Optomec expands aerosol jet lab for 3D semiconductor packaging, PV, other device formation

Thu, 1 Jan 2012

Optomec opened its new and expanded Advanced Applications Lab and Product Development Facility in St. Paul, MN. The facility will help Optomec grow its Aerosol Jet additive manufacturing technology for advanced printed electronics applications.

Semiconductor packaging houses gain from more device complexity

Wed, 1 Jan 2012

Increased I/O density, power/performance reqs, and other factors are increasing use of flip chip, 2.5D and 3D technologies, a boon to packaging subcontractors. But they face a challenge from foundries, and must navigate under-utilization of wire bonding capacity.

Upcoming SMTA events: IWLPC keynote named, SMTAI seeks presenters

Tue, 1 Jan 2012

The SMTA released its call for presenters for SMTA International (SMTAI) 2012, October 14-18 in Orlando, FL. The association, along with Chip Scale Review magazine, also announced the keynote for the International Wafer-level Packaging Conference (IWLPC), held November 5-8, San Jose, CA.

Teledyne Microelectronics to package Zephyr Photonics VCSELs

Tue, 1 Jan 2012

Teledyne Microelectronic Technologies will expand its optical packaging portfolio in a partnership with Zephyr Photonics, which makes a proprietary high-temp vertical-cavity surface-emitting laser (VCSEL).

Inari proposes acquisition of Amertron

Tue, 1 Jan 2012

Packaging house Inari Berhad signed an MOU to acquire Amertron Global, which operates in the Philippines and China providing microelectronics and optoelectronics manufacturing services.

JEDEC publishes wide-I/O mobile DRAM standard

Thu, 1 Jan 2012

JEDEC Solid State Technology Association released a new standard for wide I/O mobile DRAM: JESD229 Wide I/O Single Data Rate. Wide I/O mobile DRAM increases die integration -- stacking chips with TSV interconnects with a SoC -- and improves bandwidth, latency, power, weight, and form factor.

3D integration key to 22nm semiconductor devices

Mon, 1 Jan 2012

The benefits of 3D IC integration can be combined with aggressively scaled 22nm semiconductor devices, with More Moore (scaling) and More than Moore (package advances) developing in parallel but relatively independently, says Paul Lindner, EV Group (EVG).

ConFab interview: Amkor's Ron Huemoeller on 3D packaging readiness

Wed, 6 Jun 2012

Ron Huemoeller of Amkor presented in the Advanced Packaging session of Solid State Technology

@ The ConFab: Supply chain or supply web for 3D packaging?

Wed, 6 Jun 2012

With many advanced packaging processes taking place on the semiconductor wafer, the traditional supply chain of front-end fab at the foundry and back-end fab at the packaging and test house is falling apart. The ConFab session,

3D and 2.5D semiconductor packaging technologies @ The ConFab

Wed, 6 Jun 2012

As packaging has played a larger and larger role in chip performance, form factor, and capabilities, The ConFab has increased its focus on back-end processes. Cue

Xilinx relies on stacked silicon interconnect for 28Gbps FPGA

Thu, 5 May 2012

Xilinx Inc. (NASDAQ:XLNX) began shipping a 3D heterogeneous all-programmable FPGA, the Virtex-7 H580T FPGA, using its stacked silicon interconnect (SSI) technology to reach up to 16 28Gbps and 72 13.1Gbps transceiver bandwidth.

Ziptronix wafer stacking tech expands to 3D memory devices

Wed, 5 May 2012

Ziptronix Inc. is helping a 3D memory device maker replace standard die stacking with its DBI wafer-stacking technology, which has been proven in image sensor packaging.

IC package revenues outgrow unit shipments through 2016

Tue, 5 May 2012

Increased demand for product functionality is driving up IC packaging revenue faster -- a 9.8% compound annual growth rate (CAGR) -- than IC unit growth -- 7.3% CAGR 2010-2016, says New Venture Research (NVR).

Invensas debuts high-I/O PoP semiconductor packaging design

Tue, 5 May 2012

Invensas Corporation, Tessera subsidiary, debuted bond via array (BVA) technology, an ultra-high-I/O PoP semiconductor packaging alternative to wide-I/O TSV packaging.

Amkor plans semiconductor packaging and test facility in Korea

Sat, 5 May 2012

Amkor Technology Inc. (NASDAQ:AMKR) plans to build a state-of-the-art factory and global research and development center in the Incheon Free Economic Zone, which is located in the greater metropolitan area of Seoul, Korea.

"3.5D interposer technology could someday replace PCBs" -- TSMC's Doug Yu

Tue, 5 May 2012


CEA Leti adds SPTS on 3D IC line with 300mm PVD order

Wed, 2 Feb 2011

SPP Process Technology Systems (SPTS) received a follow-on purchase order from CEA-Leti for its Sigma fxP PVD system. The 300mm system will be used for advanced TSV development at Leti's new 300mm fab extension in Grenoble.

Stacked silicon interconnect is better than 3D stacking Xilinx

Tue, 2 Feb 2011

ElectroIQ caught up with Suresh Ramalingam, director of advanced package design and development at Xilinx, at the January MEPTEC luncheon, where he gave a presentation on the company's stacked silicon interconnect technology. In an interview with Debra Vogler, Ramalingam discusses SSIT in relation to die stacking and TSV.

3D integration comes in many flavors for semiconductor industry, says CEA Leti chief scientist

Wed, 2 Feb 2011

All the major semiconductor players are embracing 3D integration, says Simon Deleonibus. The CEA-Leti scientist and IEEE Fellow wants to see TSV mature and new technologies develop based on wafer bonding. He speaks with Debra Vogler.

Silicon Si interposers aim of CEA Leti SHINKO common lab

Fri, 1 Jan 2011

CEA-Leti signed a multiyear agreement with SHINKO ELECTRIC INDUSTRIES CO. LTD. to develop advanced semiconductor packaging technology. They will focus on volume production of silicon interposers.

Gate structure and 3D stacking winners will determine semiconductor industry direction

Tue, 1 Jan 2011

Arthur W. Zafiropoulo, Ultratech, sees the 20/22nm node as a competition for gate-first and gate-last proponents to discover which will lead the semiconductor industry. Device makers that master TSV chip stacking will be the winners over the course of this decade, he says. This is an online exclusive essay in SST's Forecast for 2011: Back to Reality series.

Leti on more Moore for TSV

Mon, 1 Jan 2011

Engineered substrates and 3D integration technology based on direct bonding for future More Moore and More than Moore integrated devicesLaurent Clavelier, head of solar technologies department at Leti, discusses the significance of Leti's IEDM paper #2.6 "Engineered substrates and 3D integration technology based on direct bonding for future More Moore and More than Moore integrated devices" with Debra Vogler, senior technical editor.

Packaging, assembly changes coming in next ITRS Update

Wed, 1 Jan 2011

Dr. Phil Garrou looks ahead to a laundry list of changes coming in the next ITRS Update with respect to assembly and advanced packaging, including 3D integration, interposers, and applications from medical to automotive and embedded applications.


CEA Leti ramps 300mm 3D packaging integration line

Mon, 1 Jan 2011

CEA-Leti is expanding its technology offering, ramping up one of Europe’s first 300mm lines dedicated to 3D-integration applications. The new line is dedicated to R&D and prototyping and includes 3D-oriented lithography, deep etching, dielectric deposition, metallization, wet etching, and packaging tools.

Ziptronix accuses Omnivision, TSMC of patent infringement

Fri, 1 Jan 2011

Dr. Phil Garrou takes a closer look at an IP dispute lobbed by Ziptronix against Omnivision and TSMC over low-temperature oxide bonding, used in making backside-illumination CMOS image sensors.

Interposer focus at recent RTI 3D conference

Thu, 1 Jan 2011

Fresh off 3D announcements of IBM and Samsung, several industry leaders talked about the imminent use of 3D Interposers at the RTI 3-D Architectures for Semiconductor Integration and Packaging Conference in Burlingame CA, reports Dr. Phil Garrou.

IMAPS: 3D IC toolset readiness, Cu bonding, interposer failings

Tue, 3 Mar 2011

Dr. Phil Garrou reports on several talks and trends of note from the recent IMAPS meeting and Device Packaging Conference: the readiness of 3D IC toolsets, what's holding back Cu bonding; and rumors of interposers failing thermal tests.

TSV can deal with stress says Synopsys

Mon, 3 Mar 2011

Victor Moroz discusses the strong but doable effects of stress on TSVs. TSV stress ranges are comparable to the size of the TSV, and analog behaves differently than digital. Synopsys recently presented results (part of a collaboration with imec) at a SEMATECH event.

CEA Leti IPDiA partner 3D integration for passives on Si

Mon, 3 Mar 2011

CEA-Leti and IPDiA have formed a common lab to capitalize on their complementary expertise in miniaturization and 3D integration on silicon. The common lab will develop very high-end passive components that will resist harsh environments, functional sub-mounts for LEDs, and assembly technologies.

IBM to use water cooling for future 3D IC processors

Fri, 3 Mar 2011

At the recent CeBIT Fair in Hanover Germany, IBM announced that its 3D technology to appear in its Power8 processor by 2013 will incorporate microchannel cooling.

TeraView partners with HELIOS on THz semiconductor package failure analysis

Tue, 3 Mar 2011

TeraView and HELIOS are partnering to improve semiconductor package failure analysis using terahertz technology. The technology was originally developed with Intel and isolates faults in advanced 3D semiconductor packages.

SEMATECH reports die to wafer bonding progress for 3D integration

Wed, 3 Mar 2011

SEMATECH experts reported new breakthroughs in wafer bonding at the 7th Annual Device Packaging Conference (DPC), March 7-10 in Scottsdale, AZ. Low-temp die tacking has yielded faster die-to-wafer integration.

Hynix Semiconductor joins SEMATECH 3D Interconnect Program at UAlbany NanoCollege

Wed, 3 Mar 2011

Hynix Semiconductor Inc., DRAM and flash memory supplier, joined SEMATECH's 3D Interconnect program at CNSE's Albany NanoTech Complex to address industry infrastructure and technology gaps in materials, equipment, integration and product-related issues for high-volume adoption of through silicon vias (TSV).

Present at ESTC 2012 in Amsterdam

Tue, 2 Feb 2012

Electronics System Integration Technology Conference (ESTC) 2012 seeks original papers describing research in all areas of electronic packaging, including LED packaging, flexible electronics, assembly and interconnect technologies, and more.

Georgia Tech produces 130um 3D organic semiconductor package

Thu, 2 Feb 2012

Georgia Tech

X-FAB Silicon Foundries adopts SFT software

Fri, 2 Feb 2012

X-FAB Silicon Foundries, a More-than-Moore semiconductor foundry, has used SFT's R3D (Resistive 3D) software for its 0.18

CEA-Leti launches 3D semiconductor packaging platform

Tue, 1 Jan 2012

CEA-Leti launched a major new platform, Open 3D, that provides industrial and academic partners with a global offer of mature 3D packaging technologies for their advanced semiconductor products and research projects.

USPTO seeks nominees for National Medal of Technology and Innovation

Tue, 1 Jan 2012

The USPTO is looking to increase the diversity of honorees for its annual National Medal of Technology and Innovation (NMTI), honoring "this nation's creative geniuses."

Sony stacks CMOS image sensor pixel structures and chips

Mon, 1 Jan 2012

Sony has developed a backside-illuminated CMOS image sensor that layers the pixel section with back-illuminated structures over the chips containing signal processing circuits, instead of using supporting substrates.

Lifting the veil on silicon interposer pricing

Mon, 12 Dec 2012

Are we closer than we think to our needed mass production costs for silicon interposers? Phil Garrou gleans some insights from the year-ending RTI Architectures for Semiconductor Integration and Packaging conference.

Singapore IME launches 2.5D silicon interposer MPW

Wed, 12 Dec 2012

Singapore's Institute of Microelectronics (IME) has launched a new multiproject wafer service for 2.5D through-silicon interposers, to provide a cost-effective platform for R&D prototyping and proof-of-concept in the technology.

Tezzaron licenses Ziptronix's bonding tech for 3D memory

Mon, 12 Dec 2012

Tezzaron Semiconductor has licensed patents regarding Ziptronix's direct bonding technologies, "direct bond interconnect" (DBI) and "direct oxide bonding (ZiBond), for use in 3D memory.

Will the $2 interposer be silicon or glass?

Tue, 11 Nov 2012

Dr. Phil Garrou reports from the 2nd annual Georgia Tech 2.5D Interposer Conference: what's the market projection for silicon and glass interposers, what's preventing high-volume manufacturing, and is there a crossover with flat-panel display glass manufacturing?

Alchimer pursuing partners with new CEO, CTO

Tue, 11 Nov 2012

Alchimer SA says it is seeking partnerships with various semiconductor equipment and materials companies as it welcomes two top execs: Bruno Morel is the company's CEO since May of this year, and product development director Fr

Imec's via-middle TSV fab 'reveals' contacts by wafer thinning/etch

Tue, 3 Mar 2012

Imec developed a via-middle approach to through-silicon via (TSV) manufacturing for 3D packaging, using wafer thinning and a silicon etch process to reveal TSV contacts on the wafer.

Amkor (AMKR) names Taiwan leader with semiconductor packaging background

Fri, 3 Mar 2012

Amkor Technology Inc. (Nasdaq: AMKR) added Mike Liang as president of Amkor Technology Taiwan. Liang's background includes stints with Phoenix Semiconductor, Ti-Acer, UMC, and others.

Shin-Etsu Chemical joins EVG wafer bonding supply chain

Wed, 3 Mar 2012

EV Group (EVG) welcomed Shin-Etsu Chemical  into its open platform for temporary bonding/debonding materials supporting 3D semiconductor packaging.

Interposer supply/ecosystem examined at IMAPS Device Packaging

Mon, 3 Mar 2012

Dr. Phil Garrou, a contributing editor and regular blogger on Solid State Technology, shares the highlights of an Evolving 2.5D/3D Infrastructure panel he hosted at IMAPS Device Packaging. On the table: where TSVs and interposers are made, a TSV/interposer timeline and cost analysis, and the requirements of mobile electronics.

AMAT, Singapore's microelectronics institute open 3D semiconductor packaging R&D lab

Wed, 3 Mar 2012

Applied Materials Inc. (AMAT) opened the new Centre of Excellence in Advanced Packaging at Singapore

STATS ChipPAC brings FOWLP to stacked packages for <1mm profile

Tue, 3 Mar 2012

STATS ChipPAC Ltd. (SGX-ST:STATSChP) uncrated its next-generation eWLB package-on-package (PoP) technology, with a package profile height below 1.0mm.

AMAT, A*STAR Advanced Packaging Centre of Excellence plans grand opening

Thu, 3 Mar 2012

Applied Materials and Singapore's A*STAR Institute of Microelectronics will officially open the Centre of Excellence in Advanced Packaging, in Singapore

ICECool puts 3D thermal issues back in focus

Mon, 10 Oct 2012

With the approach of full commercial production of 3DIC products, Dr. Phil Garrou shifts his attention to thermal performance questions and proposed thermal solutions for the future.

SPTS Technologies, Fraunhofer IZM researching lower-temp films for TSVs

Thu, 10 Oct 2012

Fraunhofer IZM's All Silicon System Integration Dresden (ASSID) center will add SPTS' etch and PECVD process capabilities to investigate low-temperature dielectric films for through-silicon vias (TSV) in 3D IC packaging.

Why SATS consolidation needs to happen

Fri, 10 Oct 2012

The advent of leading-edge semiconductor packaging technologies dictates efficient use of capital, and only the top-tier semiconductor assembly and test services (SATS) companies will have the financial wherewithal to develop required expertise and capacity, says one analyst.

Nanium ships 200 millionth eWLB component

Wed, 10 Oct 2012

Nanium says it has shipped its 200 millionth embedded wafer-level ball grid array technology (eWLB) component, a 10% year-over-year productivity increase that reflects full conversion to the company's eWLB overmold technology that allows thinner and more robust packages.

SPTS unveils low-temp PECVD cluster tool for 3D ICs

Wed, 9 Sep 2012

SPTS' Delta fxP cluster system achieves low-temperature deposition of TEOS oxides and nitrides for via-reveal passivation in 3D IC packaging, solving two key problems of low temperatures and bonding adhesive outgassing.

EVG updates modular coater/developer with OmniSpray, NanoSpray coating options

Mon, 9 Sep 2012

EV Group's updated modular EVG150 high-volume coater/developer adds new modules for conformal coating of high topography surfaces, and coating surfaces with vertical sidewall angles, such as through-silicon vias (TSV).

Wet process technologies for scalable through silicon vias

Fri, 4 Apr 2011
Electrografting nanotechnology has been optimized for highly conformal growth of TSV films, enabling a large reduction in cost-of-ownership per wafer compared to the dry process approach. Claudio Truzzi, Alchimer S.A., Massy, France

Tessera focuses on semiconductor technologies beyond packaging

Thu, 4 Apr 2011

Tessera Technologies Inc. (Nasdaq:TSRA - News) began two corporate initiatives to expand its technologies in semiconductor microelectronics beyond packaging, and to potentially separate its Imaging & Optics business.

Present on interposer technology

Tue, 9 Sep 2011

The first annual Global Interposer Technology Workshop at Georgia Tech will convene students, academics, researchers, and industry to share information on silicon and glass interposers for semiconductor packaging.

Xilinx, Elpida highlight SEMICON Taiwan's SiP Global Summit

Mon, 9 Sep 2011

Dr. Phil Garrou takes a closer look at highlights from a SiP summit at the recent SEMICON Taiwan: Xilinx FPGAs and Elpida's low-power DDR3 memory.

Advanced semiconductor package test emphasized at new BiTS Workshop

Fri, 9 Sep 2011

The Burn-in & Test Socket Workshop (BiTS Workshop) is changing its name to The Burn-in & Test Strategies Workshop to reflect the "evolution of packaged ICs."

Multi-die face-down packaging suits existing wire bond lines

Thu, 9 Sep 2011

Invensas Corporation, a Tessera subsidiary, will demonstrate dual-face down implementation of its new multi-die face-down packaging technology at the Intel Developer's Forum. The multi-die package is wire bonded, mounting ICs upside down and staggering them in a shingle-like configuration.

3M, IBM to make 3D chip adhesives

Wed, 9 Sep 2011

Forget "3D stacking" -- the two companies say a special electronic "glue" applied to the wafer will help stack dozens of chips into a "silicon skyscraper" that will be much faster and more efficient than current chip technology.

Alchimer TSV barrier-layer film shows 100% deposition coverage

Tue, 9 Sep 2011

Alchimer's AquiVia film-deposition technology promises to cut fill deposition times and cost even with complex through-silicon via (TSV) 3D packaging structures. The product targets TSV ramp-up at production levels, according to the company.

SUSS MicroTec sends equipment to SVTC in MEMS, 3D IC dev partnership

Tue, 11 Nov 2011

Nanotechnology accelerator SVTC Technologies partnered with SUSS MicroTec on wafer-level packaging for MEMS, and 3D IC bonding technology development.

Backside-illuminated image sensors: Optimizing manufacturing for a sensitivity payoff

Fri, 11 Nov 2011

Backside-illuminated image sensors require more precise wafer processing -- uniform extreme wafer thinning, dopant control, epitaxy growth, trench manipulation, etc. -- but the payoff in image quality is significant. Researchers at imec experimented with different wafer fab technologies to make a record BSI sensor. They also consider new architectures/packaging techniques for this technology.

Thin-film chip boosts LED optical output without changing footprint

Thu, 11 Nov 2011

OSRAM Opto Semiconductors increased its IR Power Topled with lens optical output by 80% over the standard version by integrating a thin-film chip. The IR LED maintains the same surface area and drive current.

SEMATECH creates 3D packaging standards development forum

Mon, 11 Nov 2011

SEMATECH has created an online 3D Standards Dashboard, allowing 3D semiconductor and MEMS interconnect professionals to exchange standards activity information.

Thailand flood update from key semiconductor assembly and test companies

Fri, 11 Nov 2011
Numerous global semiconductor suppliers maintain assembly and test operations in Thailand. Many of these facilities have been affected by the disaster. IHS iSuppli pulled together a list of those affected, and those that have thus-far escaped damage.

SRC attacks 3DIC reliability, design tools with new effort

Thu, 5 May 2011

Semiconductor Research Corporation is leading an effort to address key roadblocks for wide-scale adoption of the emerging 3D ICs and systems. These new initiatives will address critical reliability and design tool issues and leverage partnership between researchers from universities and the semiconductor industry.

Electronics packaging leaders gathered under cherry blossoms at ICEP

Thu, 4 Apr 2011

ASE FOWLPT.Onishi, Grand Joint Tech and E.J. Vardaman, TechSearch International share the highlights on low-k dielectrics, 3D packaging, copper pillar, and other exciting work presented at the International Conference on Electronics Packaging (ICEP) in Japan.

Silicon interposer cost redux goal of GA Tech consortium

Wed, 4 Apr 2011

Georgia Tech PRC believes current silicon interposers are limited in performance by high electrical loss of silicon and high cost of wafer-based interposers. Georgia Tech PRC has undertaken silicon R&D with the potential to reduce the cost by 5-10x, in the Silicon and Glass Interposer Industry (SiGI) Consortium.

CEA Leti deploys EVG's litho, packaging tools for 300mm line

Tue, 4 Apr 2011

CEA-Leti has installed multiple EVG tools in its 300-mm cleanroom dedicated to R&D and prototyping for 3D integration applications. EVG's equipment will be used in 3D technology demonstrations for Leti's global customer base, as well as low-volume pilot production on 300mm wafers.

STATS ChipPAC expands TSV service with mid end flow

Tue, 4 Apr 2011

STATS ChipPAC Ltd. (SGX-ST: STATSChP), semiconductor test and advanced packaging service provider, is expanding its 300mm through silicon via (TSV) offering with the addition of mid-end manufacturing capabilities.

3D IC is only solution for scaling "up," says MonolithIC 3D exec

Thu, 3 Mar 2011

Transfer on top of processed wafer and replace gates (<400°C)Zvi Or-Bach, MonolithIC 3D, describes the TSV-beating monolithic IC fab process, and argues for scaling "up" rather than down. Or-Bach compares the costs of further semiconductor scaling to advanced packaging.

If wide I/O DRAM and other 3D technologies can go HVM standards are needed

Wed, 3 Mar 2011

Mechanical stresses can prevent successful implementation of 3D packaging technologies, says Larry Smith, SEMATECH. He argues for a DFM-like solution to identify and manage stress on thinned and stacked die in 3D ICs. To complicate matters, foundries, OSATs, and memory suppliers could inflict different stresses on the die, and the whole industry is too new at 3D packaging to present concrete answers.

3D CT X ray imaging fills inspection gaps says Xradia

Tue, 3 Mar 2011

Xradia microscope.Xradia has unveiled its latest micro computed tomography (CT) 3D X-ray imaging system, the VersaXRM. Kevin Fahey, PhD, VP of marketing at Xradia, discusses how the new platform uses geometrical magnification in tandem with an X-ray microscope.

TSV probe partnership Cascade Microtech imec collaborate for kgd

Thu, 3 Mar 2011

Cascade Microtech Inc. (NASDAQ: CSCD) and imec entered into a collaborative research partnership for testing and characterization of 3D integrated circuit (IC) test structures. Imec will work closely with Cascade Microtech to develop test methods and methodologies for emerging 3D through silicon via (TSV) structures, and to develop global standards.

NuPGA becomes MonolithIC 3D, expands IP in monolithic 3D semiconductor space

Thu, 3 Mar 2011

As it developed an improved FPGA technology, the NuPGA team discovered a path for practical monolithic 3D ICs. MonolithIC 3D changed its strategy to focus on monolithic 3D IC technology as a pure IP innovator organization.

Stacked semiconductor die inspection debuts from Sonix

Fri, 3 Mar 2011

Sonix SDI stacked die inspection imageSonix Inc., scanning acoustic microscope designer and manufacturer, introduced its Stacked Die Imaging (SDI) enhancement, which effectively inspects for defects in semiconductor stacked die and wafer level packages (WLP) by selectively increasing the ultrasonic signal gain for deeper interfaces of interest.

Honeywell taps Tezzaron Semiconductor to stack rad-hard die

Fri, 12 Dec 2011

Honeywell Microelectronics will use Tezzaron's 3D stacking on Honeywell

TSMC, Arteris develop silicon-interposer-based NOCs

Wed, 12 Dec 2011

Arteris Inc., network-on-chip (NoC) interconnect IP company, will incorporate its FlexNoC NoC interconnect IP into an SoC die on silicon interposer test chip with TSMC.

Silicon interposer partnership sets roadmap

Tue, 12 Dec 2011

Singapore's A*STAR IME and 3D IC developer Tezzaron Semiconductor signed a research collaboration agreement to develop and exploit advanced through silicon interposer (TSI) technology.

2.5D announcements at the Global Interposer Tech conference

Tue, 12 Dec 2011

At the recent Global Interposer Technology workshop at Georgia Tech, Xilinx and TSMC discussed 2.5D chip packaging technologies and others touted the potential of glass as an interposer substrate material, reports Dr. Phil Garrou.

IBM fabs Micron memory cube with TSV tech

Fri, 12 Dec 2011

Using the advanced through-silicon via (TSV) fabrication process at IBM (NYSE:IBM), Micron Technology Inc. (NASDAQ:MU) will begin producing its Hybrid Memory Cube. The companies claim that this is the first CMOS design to go commercial with TSV interconnects.

Leti on 3D CMOS and photonics interconnect

Mon, 11 Nov 2011


TSMC repeats call for foundry-centric 2.5/3D industry

Thu, 12 Dec 2011

The readiness of suppliers to offer 2.5D packaging technologies was in full debate at the RTI 3D ASIP event this month, with presentations and rumors questioning how soon customers will need 2.5D/3D, and whether some offerings are worth the investment.

GSA publishes 3D/2.5D packaging studies

Tue, 12 Dec 2011

The Global Semiconductor Alliance released "3D IC Architecture: A Natural Evolution," a report sponsored by Macronix International and Etron Technology. GSA also published the 2nd edition of the 3D IC Design Tools and Services Tour Guide.

Advanced package technologies' growth through 2015

Tue, 12 Dec 2011

Small, mobile, Internet-connected devices are bucking the slow economy and use advanced packaging technologies to pack an enormous amount of functionality into a very small form factor, notes New Venture Research, which provides forecasts for each advanced packaging device type.

Powertech seeks 30-51% of Greatek

Mon, 12 Dec 2011

Powertech Technology Inc. (PTI) has approved a tender offer of NT$25.28 per share for the common shares of Greatek with a minimum acquisition target of 30% of outstanding shares.

ITRI brings 3D packaging expertise to Rambus partnership

Thu, 12 Dec 2011

Licensing company Rambus Inc. (Nasdaq:RMBS) is engaging with the Industrial Technology Research Institute (ITRI) in Taiwan on the development of interconnect and 3D packaging technologies.

Silicon interposers: building blocks for 3D-ICs

Wed, 6 Jun 2011
Silicon interposers seem set to stay as a valid alternative implementation to full 3D-IC designs. Matthew Hogan, Mentor Graphics, Wilsonville, OR

3D IC prototyping process result of MENT, Tezzaron, MOSIS collaboration

Thu, 6 Jun 2011

Mentor Graphics Corporation (NASDAQ:MENT), in a cooperative effort with Tezzaron Semiconductor and MOSIS, created a process for economically developing and manufacturing 3D-IC prototypes on multi-project wafers (MPWs).

IMEC, Cadence automate 3D IC design test

Mon, 6 Jun 2011

Imec and Cadence say they have developed a design-for-test and automatic test pattern generation technology to more easily test 3D stacked ICs with through-silicon via (TSV) functionality, adding only "negligible" area costs.

Elpida, PTI, UMC finalize 3D IC partnership

Wed, 6 Jun 2011

Updating on plans announced a year ago, Elpida, Powertech, and UMC say they have finalized their partnership to develop a "one-chip" logic+DRAM 3D IC solution incorporating 28nm interface design, through-silicon via (TSV) formation, wafer thinning, testing, and chip stacking assembly.

FEI plasma FIB tool targets packaging apps

Mon, 6 Jun 2011

High-speed sectioning of TSVs with plasma FIB. The device was located, cross-sectioned, polished, and imaged with PFIB. SOURCE: FEI FEI's new Vion plasma focused ion beam (PFIB) system based on inductively-coupled plasma (ICP) source technology using a xenon ion beam generates more than a micro-amp of beam current and can remove material faster than liquid metal ion sources, says product marketing manager Peter Carleson.

More Moore & More than Moore require fabless, foundry, and packaging houses on board

Tue, 5 May 2011

Complex supply chain. SOURCE: Yu, The ConFabToday at The ConFab, John Chen (Nvidia), Jeong-ki Min (Samsung Electronics), and Abraham Yee (Nvidia) gathered foundry, OSAT, and chip maker leaders to discuss what happens beyond Moore's Law. The following are key points from "Collaboration to Strengthen the IC Supply Chain."

Asian foundry inspects micro bumps with Camtek systems

Thu, 5 May 2011

Camtek Ltd. (NASDAQ and TASE: CAMT) received repeat automatic optical inspection (AOI) orders from an Asia-based foundry doing advanced micro bump inspection and metrology. Challenges arise in measuring such small bumps used in advanced packages, including efficiently handling huge amounts of data.

STATS ChipPAC widens fan-out WLP configurations with TSVs, IPDs

Tue, 5 May 2011

STATS ChipPAC says integrating through-silicon vias with passive devices and its eWLB technology addresses complex design issues, shrinking lithography nodes, and increased performance demands for mobile and consumer applications.

3D stacked IC design flow gets boost from imec, Atrenta partnership

Wed, 5 May 2011

imec's 3D integration industrial affiliation program (IIAP) partnered with Atrenta Inc., SoC realization products provider to semiconductor and electronic systems industries, to developed an advanced planning and partitioning design flow for heterogeneous 3D stacked ICs.

Will PoP delay TSV adoption? TechSearch International analyzes the 3D technologies

Thu, 5 May 2011

PoP provides a cost/performance solution that solves business and logistics issues associated with stacking devices directly. 3D TSV, with its associated uncertainties, cannot yet meet PoP's benefits, says TechSearch International (TSI).

Alchimer wet deposition debut targets RDL, other 3D IC processes

Wed, 5 May 2011

Alchimer's wet-deposition process, AquiVantage, grows interconnect layers for interposer redistribution layers (RDLs) and significantly enhances via-last backside wafer interconnects. The process eliminates 2 costly photolithography steps.

AMKR senior notes offering draws $400M

Mon, 5 May 2011

Amkor Technology (NASDAQ:AMKR) completed its offering of $400 million aggregate principal amount of its 6.625% Senior Notes due 2021. The proceeds from the offering will be used to fund the company's tender offer for the approximately $264.3 million aggregate principal amount of its outstanding 9.25% Senior Notes due 2016, for general corporate purposes.

3D integration: Bringing it home with supply-chain buy-in

Thu, 5 May 2011

A recurring theme at this year's Confab is that 3D integration shows tremendous promise, particularly with many fabless companies, yet many barriers remain -- and the first and biggest is preparing the supply chain.

Non-planar device scaling: SEMATECH talks TSV, SoC, SiP

Thu, 5 May 2011

The semiconductor industry is moving to 3D device structures, says Raj Jammy, SEMATECH, at The ConFab 2011, discussing TSV and system-in-package (SiP) opportunities and challenges. He also summarizes logic and memory roadmaps.

3D packaging disrupts the IC supply chain -- ConFab session dedicated to the OSAT/foundry/fabless relationship

Fri, 5 May 2011

The ConFab gathers semiconductor industry leaders to discuss the biggest trends in the chip manufacturing sector. One of these major trends is 3D packaging, and Session 2 on Monday (May 16) will combine packaging house, fabless, and foundry approaches to the new supply chain, with speakers from Amkor, GLOBALFOUNDRIES, STATS ChipPAC, and Qualcomm.

Tessera receives initial Amkor payment in court award

Tue, 8 Aug 2012

Tessera received an initial payment of approximately $20 million from semiconductor packaging company Amkor, related to the interim award issued by the International Court of Arbitration of the International Chamber of Commerce (ICC).

Hybrid Memory Cube interface specification draft includes protocol, short-reach PHY interconnection

Wed, 8 Aug 2012

The Hybrid Memory Cube Consortium released the initial draft of the Hybrid Memory Cube (HMC) interface specification, with the final version planned for end of 2012.

Flooding in the Philippines threatens microelectronics facilities

Thu, 8 Aug 2012

Heavy monsoons moving through the Philippines are causing floods in and around Manila, the capital. The Philippines is a small but growing area for microelectronics manufacturing and packaging facilities.

Nanya implements 3D IC TSV technology for DDR3, future DDR4 devices

Fri, 7 Jul 2012

Dr. Phil Garrou, contributing editor, shares Nanya Technology

3D TSV Summit planned for European semiconductor industry

Wed, 7 Jul 2012

SEMI Europe will host a new event, the European 3D TSV Summit, January 22-23, 2013 in Grenoble, France. This inaugural meeting will revolve around the theme: "On the Road towards TSV Manufacturing," denoting how device designers and manufacturers are crossing from 2D packaging to 3D for more functionality in a smaller form factor.

STATS ChipPAC adds director with experience from Intel to Zarlink

Wed, 7 Jul 2012

STATS ChipPAC appointed Gary Tanner as a member to its Board of Directors. Tanner brings experience from Zarlink Semiconductor, Intel, Texas Instruments, and other semiconductor companies.

New MEMS, 3D IC packaging working group chairs at GSA

Tue, 7 Jul 2012

Global Semiconductor Alliance (GSA) recently named Jay Esfandyari, STMicroelectronics, as its MEMS Working Group chairman and Ken Potts, Cadence Design Systems, as the 3D IC Working Group chairman.

3D TSV packages outgrow semiconductor industry by 10X

Thu, 7 Jul 2012

3D TSV chips will represent 9% of the total semiconductors value in 2017, according to Yole D

Ziptronix wafer bonding technology adopted for high-volume cellphone component

Tue, 7 Jul 2012

Ziptronix Inc., which develops direct bonding technology for advanced semiconductor applications, has licensed its technology for a high-volume cellular handset application.

2012 ITRS update: Back-end packaging and MEMS

Fri, 7 Jul 2012

At SEMICON West, the working groups of the International Technology Roadmap for Semiconductors (ITRS) outlined 2012 updates to the roadmap. Check out the back-end process info here.

Video: Readiness of 3D technologies from a materials perspective

Fri, 7 Jul 2010

Mark Privett, Brewer Science, says that new technologies allow use of higher temperatures as well as room-temperature processes, such as wafer de-bonding. The 3D industry is nearly ready for high-volume, yet still without industry standards.

Insights from SEMICON: Video interview with blogger Phil Garrou

Wed, 7 Jul 2010

In this video interview, Philip Garrou, microelectronics consultant and Advanced Packaging blogger, offers information on his blog, Insights from the leading edge, and summarizes reasonable roadmaps for 3D technology and TSV in particular. 2012 mainstream adoption seems too aggressive to Garrou.

EDA in a 3D semiconductor world: Walden Rhines

Tue, 7 Jul 2010

In this video interview from SEMICON West 2010, Walden Rhines, Mentor Graphics, discusses 3D technologies. EDA tools need to be extended to meet the needs of 3D -- parasitic extraction and timing, place-and-route, and other steps are different with 3D. The tools are evolving for the various 3D technologies. He also touches on lithography evolution.

Workshop addresses simulating, measuring 3D IC stress using TSVs

Tue, 7 Jul 2010

SEMATECH and Fraunhofer IZFP hosted a follow-up meeting in conjunction with SEMICON West (Tuesday, July 13) to evaluate a design-for-manufacturing (DFM) approach to managing stress in 3D interconnects, and to drive consensus and support for these techniques across the industry.

TSV infrastructure and standardization questions with Matt Nowak

Tue, 7 Jul 2010

In this video, Matt Nowak, Qualcomm, talks about his keynote at ASMC on through silicon technologies for stacking die in advanced packaging applications.

Take the survey on PoP assembly

Fri, 7 Jul 2010

Package on package (PoP) stacking makes use of the vertical space available on electronics printed circuit boards (PCBs). It increases density, fitting more silicon into the same footprint. However, package stacking can be difficult, as fine pitches require placement accuracy, and taller stacks generally face reliability issues, especially if the stack is reflowed improperly. So where should PoP stacking take place?

SEMICON West Lesson #3: 3D and packaging are hot

Mon, 7 Jul 2010

Wrap-up of what we heard and saw at SEMICON West 2010. Lesson 3: Everything about 3D & packaging was hot, with suppliers jostling to get into this next high-growth market. But are they really prepared for what awaits them?

Lasertec joins SEMATECH 3D packaging research, installs 300mm TSV IR etch metrology tool

Thu, 7 Jul 2010

Lasertec joined SEMATECH’s 3D Interconnect program to develop robust, cost-effective process metrology technology solutions for readying high-volume via-mid through silicon via (TSV) manufacturing. This article includes a video interview with SEMATECH about the partnership.

SEMI forms 3D stacked IC standards group, seeks volunteers

Tue, 12 Dec 2010

SEMI International is forming a standards committee to evaluate and create specifications and practices for 3D stacked ICs (3DS-IC), with initial efforts targeting three areas: bonded wafers, inspection/metrology, and thin wafer handling.

Cu protrusion, keep-out zones highlight 3D talks at IEDM

Wed, 12 Dec 2010

Dr. Phil Garrou looks at 3D IC technology discussions at IEDM 2010, including details of TSMC's integration of 3D into its advanced CMOS foundry processes, and a close examination of 3D-induced stresses.


Wed, 12 Dec 2010

Innovative Micro Technology Inc. (IMT) added a new geometry point in its technology roadmap for through silicon vias (TSVs). Joining the copper-filled 15 by 60um depth TSV configuration that has been in production for nearly 2 years, 50 by 250um copper-filled TSV is planned for production at the beginning of 2011.


Sat, 12 Dec 2010

AT&S debuted a new technology to enable system-in-package (SiP) devices. AT&S’s embedded component packaging technology ECP is used to enable further miniaturiztion of electronic devices while enhancing their performance.

Why 3D-IC conversion resembles the bipolar-CMOS shift

Wed, 12 Dec 2010

3D IC technology will require significant changes across the design, tool, and manufacturing spectrum -- that sounds a lot like how the industry transitioned from bipolar to CMOS, writes Dr. Phil Garrou, reporting from themes at an IEEE 3D event in Munich.

SEMATECH, SIA, SRC pursuing 3D standards

Tue, 12 Dec 2010

SEMATECH, the SIA, and SRC have established a new 3D Enablement program targeting standards in inspection, metrology, microbumping, bonding, and thin wafer and die handling.

Logic apps for Si interposers and embedded capacitors: ALLVIA talk at 3D Packaging Forum

Mon, 12 Dec 2010

Dr. Nagesh Vodrahalli, vice president of technology and manufacturing at ALLVIA, will present a discussion on December 9 titled "Silicon Interposers with TSVs and Embedded Capacitors for Advanced Logic Applications."

Leveraging 3D packaging technologies: Tessera shares its latest work

Fri, 7 Jul 2010

In this video interview, Craig Mitchell, Tessera, comments on 3D packaging and interconnect. The chip industry is using packaging technologies to address miniaturization and density. Materials are posing a challenge.

Embedded wafer-level packages: Fan-out WLP/chip embedding in substrate 2010 report

Tue, 7 Jul 2010

This report from Research and Markets covers new and established technologies for embedded package integration. Benefits of embedded package integration include miniaturization, improvement of electrical and thermal performance, cost reduction and simplification of logistic for OEMs.  

Advanced packaging technologies: Imbedding components for increased reliability

Tue, 4 Apr 2010

Imbedded component/die technology is a method of imbedding active and passives into cavities within a multi-layer PCB to decrease the surface area required to implement the circuit design and increase the robustness of the overall assembly. Casey H. Cooper, STI, discusses the design methodology, packaging processes, and test data gathered during imbedded die/component packaging implementation in a mixed-signal prototype. The prototype was subjected to reliability testing and demonstrated in a test flight.

KGD Packaging and Test Workshop keynote, panel on TSV, and more

Wed, 9 Sep 2010

KGD (Known Good Die) Packaging and Test Workshop 2010 will focus on semiconductor die products test, assembly, manufacturing, and business issues in the microelectronics industry. Bill Bottoms will keynote, covering deep submicron and 3D integration.

3D Integration: The Challenges Ahead

Sun, 8 Aug 2010
The potential benefits of 3D integration -- where chips are thinned, stacked and electrically connected with through-silicon vias (TSVs)

3D ICs in the spotlight at IMAPS

Thu, 11 Nov 2010

Talks at the recent IMAPS annual meeting in Raleigh, NC put 3D ICs and through-silicon vias under the spotlight, reports Dr. Phil Garrou -- lowering costs, fixing test problems, developing standards, and who will eventually pay for it all (hello memory!).

SMTA announces IWLPC featured tutorials

Thu, 8 Aug 2010

Tutorials at the October event will cover 3D packaging, future interconnects, WLP, flip chip, and more.

PoP rework: Process control and using the right materials increases yield

Mon, 9 Sep 2010

POP after package rework.PoP packages present some unique rework challenges, such as how to rework an underfilled package; also, these packages are prone to warpage. Inspecting the area array devices can be a challenge. Bob Wettermann, BEST Inc., discusses rework solutions.

Focus on 3D TEST at IEEE Workshop

Wed, 12 Dec 2010

The test community is embracing 3D ICs, as evidenced by presentations at the first IEEE International Workshop on Testing 3D stacked ICs that addressed a range of test challenges and solutions, reports Dr. Phil Garrou.


Fri, 11 Nov 2010

TSMC packaging interviewDi Ma spoke with Debra Vogler, senior technical editor, ElectroIQ, about TSMC's work with silicon interposers, die stacking with through-silicon vias (TSV), and gate-last transistor fab.


Wed, 11 Nov 2010

In his keynote address at the MEPTEC Semiconductor Packaging Roadmaps conference, Bill Bottoms, chairman of Third Millennium Test Solutions (3MTS), gave attendees a dose of reality as he summarized the predicament facing the industry as it pursues 3D ICs. "Everything becomes more difficult at deep sub-micron," said Bottoms.

FDSOI-to-TSV-IEDM-preview-CEA-Leti research

Tue, 11 Nov 2010

CEA-Leti will present 10 papers, including two invited papers, at the IEDM/IEEE 2010 International Electron Devices Meeting December 6-8, in San Francisco, CA. The papers will cover More than Moore, FDSOI, memory (phase-change and charge-trapping), silicon nanowires, TSVs, high-k dielectrics, and more.


Mon, 11 Nov 2010

In this podcast interview, Smith discusses the three generations in the transition to 3D packaging and how the OSATs shape the development roadmap. Smith says that we need complete supply chain collaboration: EDA tool suppliers, equipment/materials suppliers, logic, memory, fabless, IDMs, and the SATs, to develop and deploy the technologies.

Flip chip PoP is perfect for mobile, if done right

Wed, 11 Nov 2010

Craig Mitchell, TesseraPackage-on-package, implemented with flip chip package assembly, is meeting requirements for next-gen mobile devices. Challenges remain: fine pitch underfill, brittleness of ultra low-k (ULK) dielectrics, and shorting between adjacent bumps. Craig Mitchell, Tessera, examines the lucrative 3D packaging step and how to face these challenges.


Mon, 11 Nov 2010

Advanced Packaging asked our readers where -- at the foundry, in a dedicated semiconductor assembly and test services (SATS) house, or on the SMT line -- package-on-package (POP) assembly should take place.


Tue, 11 Nov 2010

Rudolph’s NSX Series Macro Defect Inspection Systems Rudolph Technologies Inc. (RTEC) is partnering with a major outsourced semiconductor assembly and test (OSAT) services manufacturer to provide its inspection and metrology capability in the development of stacked packaging processes. The process uses silicon interposer technology, sometimes referred to as 2.5D IC, as an intermediate step toward full blown 3D ICs.


Tue, 11 Nov 2010

Alchimer's Electrografting (eG) technology has been validated by scientists at RTI International (RTI). The paper confirmed that electrografting is a proven technology for depositing "insulator, barrier and seedlayer into high aspect ratio TSVs for 3D integration applications."

Allvia completes tests for stacked-semi Si interposer

Fri, 1 Jan 2010

Allvia says it has completed integration and full reliability testing of a silicon interposer between a semiconductor die and an organic or ceramic substrate.

SMTA webcasts on package on package (PoP), STACK assembly, rework, and inspection

Fri, 1 Jan 2010

The Surface Mount Technology Association (SMTA) will host two 90-minute online sessions with Bob Willis, ASKbobwillis.com, on package-on-package (PoP) applications and implementation. The Webtorials will take place February 4 and February 11, 2010 from 1:00 to 2:30 pm EST.

Henkel develops wafer backside coating for die attach

Mon, 8 Aug 2010

Henkel has extended its Wafer Backside Coating (WBC) portfolio to also include a solution for stacked-die packages. Ablestik WBC-8901UV has been designed to address the demanding requirements of multiple die stack applications for the memory market segment.

Convergence of 3D integrated packaging and 3D TSV ICs

Sun, 8 Aug 2010
As the need to integrate MEMS devices and advanced memory for sensor applications expands, work is underway to develop modules merging both mechanical and electrical devices into single, highly compact modules. Navjot Chhabra, Freescale Semiconductor, Austin, Texas, USA

Process equipment readiness for through-silicon via technologies

Sun, 8 Aug 2010
Unit processes, integration schemes, and equipment are in place to enable development and pilot production of TSV technologies and all parts of the value chain do exist today at 300mm to enable integration technology qualification, end-product samples, and limited pilot production. Sesh Ramaswami, Applied Materials, Santa Clara, CA USA

TSV: Current challenges and solutions with Novellus

Fri, 8 Aug 2010

In this video interview, Sesha Varadarajan, Novellus, says that capacitance issues must be overcome, and the PVD step must provide good enough coverage to properly apply copper. CTE mismatch can also cause issues.

Si, glass interposers for 3D packaging: analysts' takes

Tue, 8 Aug 2010

Silicon interposers for advanced packaging Yole reportYole asks if next-generation package substrates are myth, niche, or high-volume necessity? Several companies are investigating silicon interposers and there is great interest in the topic, but there is no clear consensus on apps and timing for adoption, says TSI in its forecast for Si interposers. Both analyst forecasts are summarized.

Look for TSV to take off in 2012: Jan Vardaman

Tue, 8 Aug 2010

In this video interview from SEMICON West 2010, Jan Vardaman, president/founder of TechSearch International, discusses 3D technologies in the real engineering world. Especially for 300mm, work is being done on processes and yield. She points to 2012 for widespread adoption of TSV.

Achieving cost and performance goals using 3D semiconductor packaging

Sun, 8 Aug 2010
It has been proven that SoC and 3D multiple die packaging can significantly improve performance and the function-to-area ratio, however, one must look at the tradeoffs. Vern Solberg, STC-Madison, Madison, WI USA

Fraunhofer's Ramm will open International Wafer-Level Packaging Conference

Tue, 8 Aug 2010

Peter Ramm, Fraunhofer EMFT, will be the Opening Speaker at the 7th Annual International Wafer-Level Packaging Conference (IWLPC). Ramm will present "The European 3D Technology Platform for Heterogeneous Systems" at the Kick-Off Reception.

Roadmapping More than Moore: When the application matters

Fri, 7 Jul 2012

At the ITRS 2012 update, back-end technologies session, at SEMICON West, roadmapping for More than Moore was addressed as both a philosophical and technical matter.

EVG's wafer bonder passes SEMATECH/ISMI 3D integration tool assessment

Wed, 7 Jul 2012

SEMATECH qualified EVG's GEMINI automated wafer bonding system through its Equipment Maturity Assessment implemented within SEMATECH's 3D Interconnect program and ISMI's EMA team.

STATS ChipPAC ramps advanced flip chips to HVM, adds TCB processing capability

Tue, 7 Jul 2012

STATS ChipPAC brought its fcCuBE advanced flip chip semiconductor packaging technology with copper column bumps, bond-on-lead interconnection, and enhanced assembly processes into high-volume manufacturing for multiple customers.

Xilinx boosts silicon and electronics engineering in Ireland

Thu, 7 Jul 2012

Xilinx will invest $50 million to expand its electronics engineering operations, located at the company

Tessera: Adding Vista Point Technologies, losing Powertech Technology?

Mon, 7 Jul 2012

Tessera received notice from Powertech Technology Inc. (PTI) that it will terminate its license agreement with the semiconductor packaging and optics technology company. Tessera also completed phase 1 of its acquisition of camera module technologies from Flextronics.

Unisem focuses new business model on Tier-1 customers and high-value technologies

Fri, 6 Jun 2012

UNISEM relaunched its business model with the name

Ultratech acquires IBM patents for semiconductor packaging processes

Fri, 6 Jun 2012

Ultratech acquired IBM patents on semiconductor packaging technologies, including C4 bumping, ball grid array (BGA) methods, lead-free solders, and 3D packaging.

3D and 2.5D Integration: A Status Report preview with TechSearch International

Tue, 6 Jun 2012

Solid State Technology is hosting 3D and 2.5D Integration: A Status Report, sponsored by EVG and ALLVIA, and is free for all attendees. This preview shares a sneak peek at

Xilinx speaker joins 3D packaging webcast roster

Tue, 6 Jun 2012

Solid State Technology is hosting a free webcast, 3D and 2.5D Integration: A Status Report. A fourth presenter has just been announced, Brent Przybus, Senior Director, Product Line Marketing, Xilinx Inc.

Dow Corning teams with SUSS on TSV bonding process

Mon, 6 Jun 2012

Dow Corning will collaborate with SUSS MicroTec on a temporary bonding process (materials and equipment) for through-silicon vias (TSV) in high-volume advanced semiconductor packaging.

New speaker added for 3D and 2.5D Integration webcast

Mon, 6 Jun 2012

Solid State Technology will present 3D and 2.5D Integration: A Status Report on June 27, free for all attendees. William Chen, ASE, will join speakers David McCann, GLOBALFOUNDRIES and E. Jan Vardaman, TechSearch International.

DARPA seeks microfluidic thermal management for 3D ICs

Mon, 6 Jun 2012



Fri, 6 Jun 2012

Attendance was high at this year's Electronic Component Technology Conference (ECTC) in San Diego. Sandra Winkler is senior industry analyst at New Venture Research and IEEE/CPMT Luncheon Program Chair, shares the key trends in ECTC's sessions, like WLP, 2.5D, LED packaging, and more.

USI process produces copper-filled vias on ceramic substrates

Tue, 6 Jun 2012

UltraSource Inc. announced CopperVia, a process that fills vias with pure copper to yield low-cost, high-conductivity, reliable electrical and thermal interconnects in ceramic thin film circuit substrates.

ESCATEC offers package-on-package stacking for low-volume designs

Tue, 6 Jun 2012

ESCATEC added package-on-package (PoP) capability at its Heerbrugg, Switzerland, facility, adding a dipping unit for ball grid array (BGA) packages on its Siplace assembly line.

ams offers foundry customers KGD with enhanced IC test

Mon, 6 Jun 2012

The Full Service Foundry business unit of ams extended its dedicated test solutions for foundry customers, offering known good die (KGD), with customers' complex analog/mixed-signal ICs 100% electrically tested according to their own test specification.

Advantest tackles 3D package test with new product line

Fri, 6 Jun 2012

Advantest is developing a line of fully automated and integrated test and handling solutions for TSV-based 2.5D and 3D packages. The concept model test cell, DIMENSION, integrates a high parallel test cluster along with singulated die and 3D die stack automated handling capabilities.

UMC developing TSV tech for BSI CMOS image sensors with A*STAR

Fri, 6 Jun 2012


Conference report: IITC closes with talks from EUV to TSV

Thu, 6 Jun 2012

Day 3 of the 15th IITC (International Interconnect Technology Conference) opened in San Jose, CA under clear sunny skies and a pleasant breeze. The herd thinned a bit, down to ~150 hearty souls from the original 230 the prior two days.

Via-last 3D packaging and interposer metallization costs chat

Thu, 7 Jul 2011

Steve Lerner, CEO of Alchimer, discusses the company's latest suite of through silicon via (TSV) technologies, focusing on how the platform reduces costs for advanced packaging processes.

SEMICON West workshop addresses stress management for 3D ICs using TSVs

Tue, 7 Jul 2011

Speakers at a SEMATECH/Fraunhofer-hosted workshop at SEMICON West looked at stress management for 3D ICS using TSVs: the state of reliability testing, failure analysis techniques, and why an engineering paradigm shift is needed.

SEMATECH survey on 2.5D, 3D IC; gaps in the via-mid ecosystem

Thu, 7 Jul 2011

Sitaram Arkalgud, director of interconnect at SEMATECH, discusses the high-volume manufacturability issues and gaps in both 2.5D and 3D semiconductor technologies with respect to backside processing and wafer bonding, thinning, and handling. Standards are also covered.

MHI 8" wafer bonder produces 3D LSI ICs at room temp with FAB gun

Wed, 7 Jul 2011
Mitsubishi Heavy Industries Ltd. (MHI) developed a fully automated 8" wafer bonding machine that bonds large-scale integration (LSI) circuits at room temperature, creating 3D ICs.

EV Group joins Ga. Tech's 3D packaging center

Wed, 7 Jul 2011

EV Group will contribute its know-how and technology in temporary bonding and debonding, chip-to-wafer bonding, and lithography technology to the Georgia Tech's PRC's Silicon and Glass Interposer Industry (SiGI) Consortium research program.

Elpida begins sampling 8Gb DDR3 SDRAM

Tue, 7 Jul 2011

Elpida Memory is now sampling a new 8Gb TSV DRAM consisting of four 2Gb layers based on TSV stacking technology.

Advanced packaging programs at SEMICON West emphasize holistic approach

Fri, 6 Jun 2011

SEMICON West preview: This year's SEMICON West Advanced Packaging Program is taking a broad approach, encouraging participation from across the supply chain to help keep pace with a rapidly expanding electronics market -- and in markets beyond, from automotive to aerospace and medical.

NCCAVS on 3D packaging: Bring on the TSVs

Mon, 6 Jun 2011

A standing-room crowd gathered at SEMI for a special NCCAVS usergroup meeting to hear about issues relevant to 3D packaging, including CMP for through-silicon vias (TSV), a DFM methodology for 3D TSV packaging designs, and TSV process integration challenges.

Forging a TSV supply chain in a consolidated market

Fri, 10 Oct 2010
Steve Lerner, Alchimer S.A., Massy, France

Xilinx stacked silicon interconnect creates multi-die FPGA for high density, bandwidth

Wed, 10 Oct 2010

Xilinx multi-die FPGA packageXilinx (XLNX) debuted a stacked silicon interconnect technology for breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package. The stacked silicon package suits applications that require high-transistor and logic density, as well as intense computational and bandwidth performance. This article includes a podcast interview with the company about the technology.

austriamicrosystems extends beyond standard foundry offering into advanced packaging

Thu, 10 Oct 2010

austriamicrosystems Full Service Foundry introduced "More Than Silicon," a comprehensive service and technology package that goes beyond standard foundry services. Foundry customers receive access to leading-edge technology add-ons, advanced packaging services, and dedicated support engineers to enable first-time-right designs.

Nanoplas targets 200mm MEMS and 3D TSV packaging with dry processing tool

Tue, 10 Oct 2010

Nanoplas toolNanoplas introduced a fully automatic dry-processing batch system for high-volume 200mm production. The DSB 9000A is based on Nanoplas’s High Density Radical Flux (HDRF) technology.

PVD System for 3D Packaging

Mon, 6 Jun 2009
The Applied Materials' Charger UBM PVD system was designed for under-bump metallization (UBM), redistribution layer and CMOS image sensor applications. Its linear architecture is said to more than double the wafer output of other systems. In addition, its proprietary Isani wafer treatment technology allows the UBM system to process ten times more wafers between servicing.

ECTC 2009 In Review

Mon, 6 Jun 2009
In a time when R&D is at the forefront of the industry, events like ECTC 2009 become critical for showcasing research achievements, as well as providing venues for learning about the latest developments across the spectrum of device manufacturing. With 16 professional courses, 39 sessions of 6 papers each, two poster sessions, and the opportunity to mix it up with prestigious members of academia and research institutes, calling the event informative would be an understatement.

Thin Film Measurement Tool

Fri, 5 May 2009
The MetaPULSE thin film measurement tool from Rudolph Technologies is optimized specifically for copper via fill in 3D IC applications, as well as copper damascene processes at 45nm through 22nm technology nodes and copper via fill in 3D IC applications. Copper thickness and overburden measurements are critical in optimizing the CMP process that follows deposition during through-silicon via (TSV) manufacturing.

Yole Report: Memory Packaging & Integration Trends

Fri, 5 May 2009
(May 8, 2009) LYON, France — The memory semiconductor industry is about to go through major technological changes as new integration trends and disruptive packaging technologies pave the way to the future growth, reports Yole. The study presents the end applications driving the use of 3D integrated memories and their key players. It also includes an overview of the memory packaging market, its forecasted evolutions with new applications and growth in flash and DRAM.

Professor Rao Tummala to Present Keynote at 2009 International Wafer-Level Packaging Conference (IWLPC)

Fri, 5 May 2009
(May 29, 2009) MINNEAPOLIS, MN — Professor Rao Tummala, Advanced Packaging Editorial Advisory Board Member, will keynote the 6th Annual International Wafer-Level Packaging Conference (IWLPC), October 27–30, 2009 at the Santa Clara Marriott Hotel in Santa Clara, CA.

Simplicity Leads to 3D Packaging Success

Tue, 4 Apr 2009
By Francoise von Trapp, contributing editor
3D embedded technologies just got closer to volume manufacturing. We've been hearing variations on the embedding theme for quite some time, but as of yet, none have made it to high volume manufacturing. However, one embedded solution, Imbera's integrated module board (IMB) technolog appears to be on its way, after the company's announcement of successful Series B funding, which the company expects will take it into high-volume production.

3D IC Technology: Interconnect for the 21st Century

Mon, 4 Apr 2009
By Paul Enquist and Chris Sanders, Ziptronix, Inc.
In 3D IC technology, thinned, planar circuits are stacked and interconnected using through silicon vias (TSVs). 3D ICs have the potential to alleviate scaling limitations, increase performance by reducing signal delays, and reduce cost. Enabling technologies for 3D IC include TSV formation, thinning, and alignment and bonding. Realizing the full potential of this technology requires a scaleable approach to 3D IC fabrication.

The Riley Report

Tue, 4 Apr 2009
Non-traditional Applications of Jet Dispensing
by George A. Riley, Contributing Editor
While jetting is common in semiconductor packaging, it is finding new applications in emerging fields. At the recent SMTA Pan Pacific Symposium, Alec Barbiarz of Asymtek described jetting opportunities in medical analytics, high-intensity lighting, active-matrix displays, green energy, and 3D assemblies.

Behind Brewer Science's wafer bonding work

Mon, 8 Aug 2009
(August 10, 2009) SAN FRANCISCO, CA -- Karen Twillmann, executive director of corporate marketing at Brewer Science, and Dan Wallace, the company's director of 3D packaging, discusses the advances made by the company's temporary bond adhesive for wafer bond applications.

Conference on 3D Architectures for Semiconductor Integration and Packaging

Tue, 6 Jun 2009
(June 2, 2009) RESEARCH TRIANGLE PARK, NC — The 2009 3D Architectures for Semiconductor Integration and Packaging Conference and Exhibition will bring together industry leaders to examine the practical and competitive landscape on the path to implementation of 3D integration and packaging technologies, December 9 through 11, 2009, in Burlingame, CA.

Applied's new InVia lays it on thick for 3D IC packaging

Mon, 3 Mar 2010

Kedar Sapre from Applied Materials talks with SST about the company's new Producer InVia CVD system targeting via-first/via-middle through silicon vias (TSV) for 3D IC packaging.

Novellus develops copper seed PVD process for TSV packaging

Tue, 3 Mar 2010

Novellus Systems (NASDAQ: NVLS) created an advanced copper barrier-seed physical vapor deposition (PVD) process for the emerging through-silicon-via (TSV) packaging market. The process uses Novellus’ established INOVA platform with patented hollow cathode magnetron (HCM) technology to produce highly conformal copper seed films that are reportedly four times thinner than the conventional PVD seed approaches used for TSV applications. Novellus announced that the HCM TSV process delivers excellent sidewall and bottom coverage, and enables void-free copper fill during the subsequent TSV electroplating step.

Allvia touts embedded capacitors with Si interposers, 3D stacks

Wed, 3 Mar 2010

Allvia says it has integrated embedded capacitors on silicon interposers, a key interface between silicon devices and organic substrates, achieving >1500nF/cm2 capacitance.

Lithography and wafer bonding solutions for 3D integration

Mon, 3 Mar 2010

Given the advantages and technical feasibility of through-silicon vias (TSV), the major focus now is on the manufacturability and integration of all the different building blocks for TSVs and 3D interconnects. EV Group's Thorsten Matthias et al. review advances in lithography, thin wafer processing, and wafer bonding, and the integration of all these process steps.

Alchimer, KPM Tech Sign Agreement for TSV Wet Processing Tools & Materials

Mon, 2 Feb 2010

In a deal that will generate economical new process options for the 3D integration market, Alchimer S.A., a provider of nanometric deposition technology for semiconductor interconnects and through-silicon vias (TSV), and KPM Tech Co. Ltd., a manufacturer of plating materials and systems, announced a multi-level collaboration that gives KPM Tech exclusive rights to produce chemicals in Korea for Alchimer’s technology. The agreement also includes the manufacture of various configurations of wet processing tools to support the Alchimer TSV platform.

3D Jargon

Mon, 2 Feb 2009
By Yann Guillou, ST-Ericsson Wireless and Eric Saugier, STMicroelectronics
3D Integration, through silicon via (TSV), 3D packaging, 3D TSV, 3D system-in-package (SiP), 3D system-on-chip (SoC), and 3D system-on-package (SoP) are some of the hottest topics presented at conferences or read about in popular tech magazines. All of these are definitively trendy terms; no one would argue to the contrary. So it's about time to take a serious look at 3D in its broadest meaning.

Tackling the TSV Checklist

Tue, 2 Feb 2009
by Fran

Via-first or Via-last ...a Matter of Perspective

Thu, 2 Feb 2009
By Chris Sanders, Ziptronix Inc.
The momentum building around 3D IC integration technology over the past few years makes it clear that this technology is going to happen — it's just a matter of when. There are three main components to 3D IC technology: through silicon via (TSV) formation; thinning; and bonding. The numerous process flows that exist for 3D integration are all related to the sequence in which these three processes occur.

Design Platform for 3D Stacked ICs

Tue, 2 Feb 2009
The j360 Silicon PathFinder 3D Platform from Javelin Design Automations supports 3D stacked IC design using through silicon vias (TSV). The design tool reportedly extends the Javelin PathFinding methodology and j360 Silicon PathFinder platform to support virtual chip design for co-optimization of system design and 3D interconnect-packaging technologies

Burn-in Test Socket Challenges

Thu, 2 Feb 2009
By Gail Flower, Editor-at-Large This article provides a broad review of the issues affecting socket usage: lead-free challenges, finer pitch adjustments, cost control, standardization, practical customer concerns, and improvements needed for 3D packages and other innovations on the horizon. Through conversations with industry experts, we explore a few common themes from this year's Burn-in and Test Socket Workshop (March 8 -11, 2009) in Mesa, AZ.

Allvia shows off its Si interposer data

Tue, 12 Dec 2009

Nagesh Vodrahalli, VP of technology & manufacturing at Allvia, discussed some of the issues in developing through-silicon via (TSV) technologies with Solid State Technology/Advanced Packaging in conjunction with his presentation at the recent 3-D Architectures for Semiconductor Integration and Packaging conference.

Micron sampling new NAND+DRAM multichip package

Wed, 11 Nov 2009

Micron Technology says it is now sampling a multichip package combing its 34nm-based 4Gb SLC NAND flash and 50nm-based 2Gb low-power DDR DRAM memories, a combination it says offers better cost and power savings for mobile devices.

Report: "Astonishing" evolution in 3D ICs, TSVs

Sat, 11 Nov 2009

Updates to a pair of reports from Yole Developpement aim to help better identify remaining integration challenges and high-volume production implementation strategies for 3D ICs and through-silicon vias (TSV).

Alchimer: Higher-AR TSV saves $700/wafer

Wed, 11 Nov 2009

A new study suggests that through-silicon vias (TSV) with higher aspect ratios (20:1 or 10:1, vs. 5:1) offer a significant payback by saving space on a die, up to $700 per wafer.

Allvia buys old ETEC site for manufacturing ramp

Thu, 10 Oct 2009

Specialty TSV foundry Allvia is expanding its manufacturing capabilities away from high-cost Silicon Valley to a newly-purchased facility in Oregon, a site with its own chip-equipment pedigree.

IMEC: 3D challenges, integrating DRAM on logic

Tue, 10 Oct 2009

Bart Swinnen, IMEC's director of interconnect and process technology unit, discusses with SST/AP the research center's 3D program, from its annual press event in Leuven, Belgium.

Avoiding ASIC expense and risk with SiCB technology

Mon, 10 Oct 2009

Embedded computing modules employing "silicon circuit board" technology as an alternative to expensive ASIC developments offer advantages in performance and power for integrating memory and logic -- and are a practical alternative to 3D integration due to thermal and supply chain issues, explains siXis' David Blaker.

Elpida stacks 8 DRAMs with TSV

Wed, 9 Sep 2009

Elpida Memory recently pushed vertical stacking of DRAM to new heights by connecting eight 1G chips using through-silicon vias, creating what it calls the world's largest-capacity DRAM with ~8GB of storage.

IMEC sets major step towards 3D integration of DRAM on logic

Wed, 9 Sep 2009

IMEC and its 3D integration partners have taped-out Etna, a new 3D chip integrating a commercial DRAM chip on top of a logic IC. The new 3D stack resembles as close as possible to future commercial chips. It consists of a 25µm thick logic die on top of which a commercial DRAM is stacked using through-silicon vias (TSVs) and micro-bumps.

IMAPS GBC and Device Packaging Conference in Review

Tue, 3 Mar 2009
by Fran


Thu, 10 Oct 2010

vertical die stack technologyAndrew Smith, Ventmark Technology Solutions, presents a 3D die stacking technology to address package miniaturization. Using bare die and vertical interconnect structures, this stacking technology permits the design of ultra-thin, near-CSP solutions without TSVs. Designers lacking custom ICs should look to new chip stacking technology.

3D architectures for semiconductor integration and packaging: Conference preview

Thu, 10 Oct 2010

The International Conference "3-D ARCHITECTURES FOR SEMICONDUCTOR INTEGRATION AND PACKAGING" will take place December 8-10, 2010 at the Hyatt Regency San Francisco Airport Hotel. Check out the planned keynotes and topics of the conference.

New 300mm TSV production processes aim of SPTS, CEA-Leti partnership

Wed, 10 Oct 2010

CEA-Leti and SPTS will develop advanced 300mm through-silicon via (TSV) 3D IC processes. The agreement defines their collaboration on a range of 3D TSV processes to optimize etch and deposition technologies used to create next-generation high aspect ratio TSVs.

3D roadmaps begin to converge

Mon, 10 Oct 2010

Last month's SEMICON Taiwan 3D Technology Forum shed some insight into what several foundries, assembly houses and customers are thinking about the timing for 3D interposers and full 3D IC, reports Phil Garrou.

Bart Swinnen, IMEC, Discusses TSVs

Fri, 8 Aug 2009

In this video interview from SEMICON West 2009, Bart Swinnen, reviews the established interconnect bonding and through-silicon via (TSV) technologies at the system-integration level. He also discusses the newer TSV possibilities and different application-specific TSVs.

PoP Device Reliability with Various Underfill Methods

Fri, 8 Aug 2009

Vicky Wang, Henkel Loctite (China) Co. Ltd. and Dan Maslyk, Henkel Corp. show how underfill type and strategy will be key to enabling highly reliable PoP devices. Few studies have evaluated the effects of the underfilling strategy — such as underfilling the bottom component only or underfilling both top and bottom components — or the effects of solder alloy choice on the reliability of PoPs. This article presents findings from a recent study on the drop test reliability of PoP devices as a function of underfill dispensing type and PoP ball alloy type.

BrightSpots 3D IC Forum: Summary of Discussions

Wed, 8 Aug 2009
The BrightSpots 3D IC Forum came to a close on Friday, July 24. Out of 3 topic areas covering technology progress, supply chain issues, and standards development, the discussions around technology progress were clearly the most active, both from a panelist and attendee perspective. What follows is a summary of each discussion. Where topics overlapped, and discussions were brief, the summaries have been combined into one.

Elpida, UMC, PTI partner for 3D IC packaging

Tue, 6 Jun 2010

Elpida Memory and Taiwanese chip firms Powertech Technology Inc. (PTI) and United Microelectronics Corp. (UMC) are banding together to push 3D IC integration for advanced semiconductor processes.

A Novel ACA for 3D Chip Stacking and Lead-free PCB Packaging

Fri, 6 Jun 2010

In a SiP chip stack, space constraints can lead to large parasitic inductances in the packaging. Planarity, processing, high-temperature exposure, and other factors also present challenges. A new anisotropic conductive adhesive technology could enable low-cost flexible packaging via a multi-layer particle structure. S. Manian Ramkumar, Ph.D., RIT, reviews the adhesives benefits to various levels of electronics interconnect.

Getting costs out, standards in for high-volume TSS

Thu, 5 May 2010

High-density through-silicon stacking (TSS) shows promise for very high-volume applications, but work still needs to be done to "tame" key issues in manufacturing, improve costs, and smooth out the supply-chain, said Matt Nowak, director of engineering in Qualcomm's VLSI technology group, in a presentation at The ConFab in Las Vegas.

imec, PVA Tepla demo 3D TSV void detection

Thu, 1 Jan 2013

Imec and PVA Tepla say they have achieved void detection in through-silicon vias at wafer level, after TSV copper plating, thanks to a nondestructive high-frequency scanning acoustic microscopy (SAM) technique.

Novati to use Ziptronix bonding tech for 3D assembly

Fri, 1 Jan 2013

Novati Technologies Inc. has licensed Ziptronix's direct bonding technologies, "direct bond interconnect" (DBI) and "direct oxide bonding (ZiBond), to offer 3D stacking services and test to customers.

Interposer consortium ready to expand at Georgia Tech PRC

Thu, 4 Apr 2012

After pioneering low-cost wafer- and panel-based glass and silicon interposers in Phase 1 of its SiGI consortium, Georgia Tech Packaging Research Center is beginning Phase 2 in June.

GLOBALFOUNDRIES installs TSV fab tools for 20nm stacked die

Thu, 4 Apr 2012

At its Fab 8, GLOBALFOUNDRIES is installing a special set of production tools to create TSV in 20nm wafers. 3D die stacking of leading-edge chips will enable mobile and consumer electronics.

STATS ChipPAC adds Pasquale Pistorio, STMicroelectronics leader, to Board

Mon, 4 Apr 2012

Semiconductor packaging service provider STATS ChipPAC Ltd. (SGX-ST:STATSChP) appointed Pasquale Pistorio as a member of the Board of Directors, effective immediately.

Georgia Tech targets thin 3D packaging with new consortium

Wed, 4 Apr 2012

Georgia Tech's Packaging Research Center proposes a new consortium on 3D semiconductor packaging called 3D ThinPack for ultra-miniaturized 3D heterogeneous, RF, digital and power modules in partnership with global companies.

Endicott Interconnect names David Van Rossum new CFO

Tue, 4 Apr 2012

Endicott Interconnect Technologies has appointed David W. Van Rossum to the position of Chief Financial Officer, effective immediately.

ALD enables 3D capacitors for CEA-Leti and IPDiA

Tue, 4 Apr 2012

CEA-Leti and passive component maker IPDiA developed an atomic layer deposition (ALD) process to apply medium-k dielectric layers on a metal-insulator-metal capacitor architecture, enabling 3D capacitors.

MOSAID multi-chip package stacks 16 NAND Flash die on 1 channel

Thu, 4 Apr 2012

MOSAID Technologies Inc. is sampling a 16-die stack NAND Flash device operating on a single high-performance channel, the 5126Gb HLNAND.

Georgia Tech increases interposer development work

Wed, 4 Apr 2012

Georgia Tech's Packaging Research Center is adding ultra-fine-pitch interconnect, thermal reliability, and more to its work on silicon and glass interposers for 2.5D semiconductor packaging.

Amkor licenses 3D packaging tech to SHINKO

Fri, 3 Mar 2012

Amkor Technology Inc. granted SHINKO ELECTRIC INDUSTRIES CO., LTD. (Tokyo:6967) a non-exclusive license to its proprietary Through Mold Via (TMV) semiconductor packaging technology.

Synopsys launches 3D packaging EDA line-up

Mon, 3 Mar 2012

Synopsys is combining several products into a 3D-IC initiative for semiconductor designers moving to stacked-die silicon systems in 3D packaging. The 3D-IC initiative will bring in leading IC design and manufacturing companies to work with Synopsys on a comprehensive EDA solution.

2011 ITRS: DRAM, 3D Flash, MEMS, nano scaling steal the show

Wed, 2 Feb 2012

The 2011 International Technology Roadmap for Semiconductors (ITRS) has been publicly released. Several areas of advancement are highlighted in the 2011 ITRS: DRAM and Flash memory, and MEMS.

Samsung, IBM and GlobalFoundries look to the future: A report from the Common Platform Technology Forum

Thu, 3 Mar 2012

Execs from Samsung, IBM, GlobalFoundries and ARM looked to the future at The Common Technology Platform Forum in Santa Clara. They focused on the innovation pipeline for 20nm and 14nm technology nodes, and the role that EUV, FinFETs, TSVs, CNTs and DSA will play.

Conference report: MRS Spring 2012, Day 2

Wed, 4 Apr 2012

Blogger Mike Fury reports from the MRS Spring 2012 meeting in San Francisco. Highlights from the second day: OLED TFT displays, single transistor DRAMs, silicon photonic wires, CNTs, 3D optical interconnects, graphene for RF and sensing, transparent ZnO, epidermal electronic systems, stretchable electronics, ultra-low-k dielectrics, patterning of electroceramics, PRAM (an alternative to NRAM), and inkjet printing of superconducting films.

European microelectronics fab database tracks major changes over past 5 years

Mon, 2 Feb 2012

Yole Developpement released "European Microelectronic Fabs Database & Report 2012," a database and report on the European microelectronics and microsystem manufacturing fabs, pilot lines, and major R&D organizations.

Apple shares list of suppliers

Fri, 1 Jan 2012

For the first time, Apple Inc. has publicly published a list of over 150 companies that the electronics giant says represent 97% of its procurement expenditures for materials, manufacturing, and assembly of products worldwide.

Will 22nm need a mid-node?

Mon, 1 Jan 2012

Art Zafiropoulo of Ultratech shares predictions for 22nm: that everyone will be using gate-last fabrication, that there may be a mid-node at 20nm, and that TSVs and 450mm wafers will play an important role at the new node.

22nm node semiconductors: Technical forecasts

Tue, 1 Jan 2012

Solid State Technology asked top analysts and technologists to provide insights on the transition to 22nm semiconductor devices. Read through the whole 10-forecast series, or check out the individual articles as you have time to see perspectives on lithography, device architecture, and more.

SEMATECH highlights from VLSI-TSA

Thu, 4 Apr 2012

SEMATECH experts reported on innovative processes for advanced CMOS logic and memory device technologies and 3D TSV manufacturing at the International VLSI Technology, System and Applications Symposium (VLSI-TSA).

ASMC will focus on productivity and technology challenges

Wed, 4 Apr 2012

The 23rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2012) will be held May 15-17 in Saratoga Springs, New York. The conference will feature presentations of more than 85 peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features a panel discussion on “Competing for R&D Dollars,” moderated by Solid State Technology Editor-in-Chief Pete Singer.

Conference Report: MRS Spring 2012, Day 3

Thu, 4 Apr 2012

Blogger Mike Fury reports from the MRS Spring 2012 meeting in San Francisco. Highlights from the third day: leakage and TDDB in low- κ dielectrics, flexible energy storage and conversion, Mn capping layers and diffusion barriers, hard masks for Cu interconnects, nanogenerators, Cu in RF, flexible temperature sensors, NEMS and MEMS in HDD, ZnO nanostructures, and various aspects of CMP.

Economy, fabless relationships, 450mm and more on deck at The ConFab 2012

Thu, 4 Apr 2012

The ConFab 2012, an invitation-only global conference and business meeting on semiconductor manufacturing, June 3-6 in Las Vegas, selected speakers and sessions for 2012.

Semiconductor industry expectations for 2012: Take the WWK survey

Fri, 2 Feb 2012

Wright Williams & Kelly, Inc. (WWK) opened its 2012 semiconductor industry survey on equipment and process timing. Only participants will receive the full results, free of charge.

David McCann of GLOBALFOUNDRIES to speak at The ConFab 2012

Thu, 5 May 2012

Solid State Technology is proud to announce that David McCann will speak at The ConFab 2012. David, the Senior Director for Packaging R&D at GLOBALFOUNDRIES in Malta, New York, will speak on the evolution toward silicon-based interconnect and packaging, which is having profound impact on how we think about technology development and the supply chain.

SEMICON China: Challenges and opportunities for semiconductors, emerging techs

Thu, 2 Feb 2012

SEMICON China takes place March 20-22 in Shanghai. Check out the special pavillions and events, and keynote speakers scheduled.

ISSCC round-up: 2.5D packaging for IVRs, smallest NAND flash chip, more

Wed, 2 Feb 2012

International Solid-State Circuits Conference (ISSCC) is going on now, gathering semiconductor design and device architecture presentations from research firms like imec to chip companies like IBM. Here are some highlighted presentations.

MEMS Symposium Report: Chasing 1 Trillion

Thu, 5 May 2012

The 10th Annual MEMS Technology Symposium sponsored by MEPTEC (MicroElectronics Packaging and Test Engineering Council) was held May 23 at the San Jose Holiday Inn. This year’s theme was “Sensors: A Foundation for Accelerated MEMS Market Growth to $1 Trillion.”

SEMICON Europa 2012 seeks presenters

Fri, 3 Mar 2012

SEMI is seeking papers for technical sessions and presentations at the upcoming SEMICON Europa 2012, October 9-11 in Dresden, Germany. Technical presentation abstracts are due April 30.

Apple A5X processor teardown: Bigger die, higher heat?

Thu, 3 Mar 2012

Apple’s ARM-based processors have created a point of hardware differentiation in applications processors. With the A5X, Apple is going with a much larger die at the 45nm node (shared across the 2 prior generations), shares Chipworks. It's also turned off the PoP track.

Taiwan allows higher Chinese investments in LCDs, semiconductors, fab equipment, more

Wed, 3 Mar 2012

Taiwan raised investment ceilings for Chinese investors in LCDs, semiconductors, IC assembly and test, microelectronics production equipment, and metal tool manufacturing.

Fraunhofer delivers 300mm wafer processing to North America with Axus Technology

Wed, 3 Mar 2012

Fraunhofer IZM and Fraunhofer CNT will use CMP supplier Axus Technology exclusively to provide advanced 300mm wafer process development and foundry services to North American customers.

SEMI adds session, extends abstract deadline for China chip conference

Tue, 10 Oct 2012

SEMI has extended the deadline to submit proposed papers to next spring's China Semiconductor Technology International Conference 2013, and added a new symposium on circuit design, system integration, and application.

GSA forms technology steering committee to guide working groups

Tue, 10 Oct 2012

The Global Semiconductor Alliance (GSA) says it has formed a Technology Steering Committee to help address key business and technology areas of interest to its members, and "encourage the advancement and adoption of leading technology and practices."

IEDM: Nanoelectronics provide a path beyond CMOS

Tue, 12 Dec 2012

At the International Electron Devices Meeting in San Francisco, An Chen of GLOBALFOUNDRIES presented a survey of emerging nanoelectronic devices, which he divided into two categories: Charge-based and non-charge based.

ICPT 2012: Five themes summarizing CMP work and progress

Mon, 11 Nov 2012

This year's International Conference on Planarization/CMP Technology (ICPT) encompassed five themes describing use of CMP: new device structures, equipment and methods, Cu interconnects, consumables, and new CMP methods and processes.

Advanced non-etching adhesion promoters eliminate interposer layer

Wed, 11 Nov 2012

New NEAPs are independent of the adhesion performance of various types of dielectric materials, and the new NEAP process adds surface area to the conductors.

EV Group completes cleanroom expansion, opens new R&D labs

Wed, 11 Nov 2012

EV Group has completed its expanded cleanroom IV facility at its corporate headquarters in Austria, which doubled its cleanroom space for process development and pilot production services.

STATS ChipPAC to expand in South Korea

Mon, 11 Nov 2012

STATS ChipPAC Ltd. plans to expand its semiconductor assembly and test operation in South Korea.

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IEDM 2012 slideshow: Sneak preview of 14 conference papers

Tue, 12 Dec 2012

We've scanned the entire conference program for next week's 58th annual IEEE International Electron Devices Meeting (IEDM), to present a quick sampling of some of the more intriguing papers.

Rudolph enters back-end lithography market

Thu, 12 Dec 2012

Rudolph Technologies, Inc. (Nasdaq: RTEC) has entered the back-end advanced packaging lithography market, with the acquisition of Azores Corp., and the introduction of a new 2X reduction stepper called the JetStep.

The ConFab 2012: A retrospective

Thu, 8 Aug 2012

The ConFab, Solid State Technology’s invitation-only event for the semiconductor industry, took place in June, with presenters from top companies and analyst firms. If you couldn’t be there, check out all the coverage from the event -- reports, presentations, video interviews and more.

Fabless keynote: Xilinx on programmability @ SEMICON West

Thu, 7 Jul 2012

SEMICON West’s Day 2 keynote speaker represented a fabless company: Ivo Bolsens, PhD, SVP and CTO of Xilinx presented on how programmable chips and innovative packaging can advance semiconductors.

Interviews with CEA-Leti researchers at SEMICON West

Thu, 7 Jul 2012

CEA-Leti presented research updates alongside SEMICON West this week. After the talks on device architecture, 3D and 2.5 packaging interconnects, large-scale computing and power consumption, and more, CEA-Leti’s researchers joined Solid State Technology to talk about their fields of interest.

ECTC: Focus on 3D integration and TSVs

Fri, 6 Jun 2012

A main focus of this year’s Electronic Components and Technology Conference (ECTC), held this week in San Diego, is 3D integration and through silicon vias (TSVs).

Conference Report: International Interconnect Technology Conference, IITC

Tue, 6 Jun 2012

The 15th IITC (International Interconnect Technology Conference) opened Monday, June 4 at the Doubletree Hotel in San Jose, CA. Recurring themes this year were variations on 3D and TSV, novel systems and packaging, and back end memory. Mike Fury reports.

A virtual IDM concept can unite semiconductor foundries, fabless companies, and packaging houses

Mon, 6 Jun 2012

The ConFab 2012, Solid State Technology’s invitation-only meeting of the semiconductor industry, opened today in Las Vegas with a keynote address from John Chen, PhD, VP of technology and foundry operations at Nvidia Corporation.

Chat with Intel’s Shekhar Borkar @ SEMICON West 2012: Overpowering power consumption

Wed, 7 Jul 2012

In this video interview, Intel's Shekhar Borkar shares some key topics from SEMICON West keynote: Near-threshold voltage transistor designs, 3D integration for DRAM, unconventional interconnect, and more.

Semicon West Day 1: FDSOI and TSV R&D with CEA-Leti

Wed, 7 Jul 2012

Michael A. Fury, Ph.D., reports on the opening day of SEMICON West (July 10), covering exaflop computing, FDSOI, TSV and other integration schemes, and silicon photonics with CEA-Leti.

Imec at SEMICON West: Interview with Luc Van den hove

Tue, 7 Jul 2012

Luc Van den hove, president and CEO, imec, spoke with Solid State Technology, covering imec’s major announcements and research presentations to take place during SEMICON West 2012.

Top conference reports from H1 2012

Fri, 7 Jul 2012

We at Solid State Technology have compiled the best conference reports so far this year, in the lead up to SEMICON West 2012, next week in San Francisco.

June 27th webcast on 3D integration

Wed, 6 Jun 2012

In a webcast scheduled for June 27th at 1:00 Eastern, 11:00 Pacific, David McCann of GLOBALFOUNDRIES will provide a status report on advanced packaging and 3D integration. McCann is responsible for Packaging R&D and back-end strategy and implementation at GLOBALFOUNDRIES.

A*STAR and Hitachi to collaborate on 3D ICs

Fri, 9 Sep 2012

Singapore’s A*STAR’s Institute of Microelectronics (IME), and Hitachi Chemical Co., will be collaborating on a joint research program to develop high performance material technologies for thin wafer processing for 3D IC packaging.

NIST tips "hybrid" metrology method to test chips

Thu, 9 Sep 2012

The National Institute of Standards and Technology (NIST) says it's combined scanning techniques and statistical data to both more precisely and less expensively measure features on a chip -- and two big chip firms are already on board.

Samsung breaks ground for memory manufacturing in China

Wed, 9 Sep 2012

Samsung Electronics Co., Ltd., held a groundbreaking ceremony for a major new memory fabrication line in Xi'an, China. Once completed, the new facility will make use of advanced 10-19nm technology to produce NAND flash memory chips, according to the company.

UMC, ST to develop 65nm backside CMOS image sensors

Mon, 9 Sep 2012

Singapore IME, MOSIS to offer silicon photonics wafer prototyping service

Tue, 9 Sep 2012

Singapore's Institute of Microelectronics (IME) and MOSIS have signed a memorandum of understanding (MOU) to offer a multiple-project wafer service targeting silicon integrated photonics.

Laser nanofabrication for mass production at the nanoscale

Fri, 8 Aug 2012

Laser nanofabrication can now meet the needs of submicron and nanoscale feature size manufacturing, and can operate in air, vacuum, or liquid processes. Sister publication Industrial Laser Solutions recently published Laser nanofabrication: A route toward next-generation mass production.

Supply chain readiness in an era of accelerated change

Fri, 8 Aug 2012

In this SEMI News and Views blog, Karen Savala covers EUV lithography, 450mm wafers, and 3D IC developments, based on her recent presentation at SEMICON West, “Supply Chain Readiness in an Era of Accelerated Change.”

Europe to unite research efforts in Silicon Europe cluster alliance

Mon, 10 Oct 2012

Four of the leading micro- and nanoelectronics regions in Europe are joining forces to form a cluster alliance called “Silicon Europe.”

Present on semiconductor metrology and more at ASMC 2013

Wed, 8 Aug 2012

ASMC 2013, the leading international technical conference for exploring solutions to improve collective microelectronics manufacturing expertise, has issued a call for papers.

STATS ChipPAC expands TSV work into mid-end-of-line

Wed, 8 Aug 2012

STATS ChipPAC says it has expanded its through-silicon via (TSV) capabilities with a 300mm mid-end manufacturing operation targeting mid-end-of-line semiconductor manufacturing, including microbump technology down to 40μm, temporary bond/de-bonding, backside via reveal, isolation, and metallization.

Bonding and cleaving at low temperatures

Tue, 8 Aug 2012

Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology and IP reports on recent progress on low temperature (less than 400°C) bonding and cleaving processes.

Technology licensing company Rambus restructures, creates CTO role

Thu, 8 Aug 2012

Rambus Inc. (NASDAQ:RMBS), a technology licensing company, will undergo a restructuring and related cost saving measures to cut its expenses by$30-35 million annually.

Tezzaron takes over SVTC's Austin fab amid layoff reports

Mon, 10 Oct 2012

Tezzaron Semiconductor is taking over SVTC Technologies' wafer fab in Austin, TX, amid reports that the semiconductor/MEMS development organization is cutting back activities in Austin and in California.

On-board heaters can self-heal flash memories

Thu, 9 Sep 2012

At the upcoming International Electron Device Meeting, Macronix researchers will describe how they built flash memories that could heal themselves by means of tiny onboard heaters that provide thermal annealing just at the spots where it is needed.

IEDM unveils 2012 program highlights

Mon, 9 Sep 2012

The 58th annual IEDM will take place December 10-12, 2012 at the San Francisco Hilton Union Square, preceded by a full day of Short Courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.

Horizontal channels key to ultra-small 3D NAND

Thu, 9 Sep 2012

The first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers at this year’s International Electron Devices Meeting (IEDM).

RRAM synapses mimic the brain

Thu, 9 Sep 2012

At this year’s IEDM, a team led by Korea’s Gwangju Institute of Science and Technology will detail a high-speed pattern-recognition system comprising CMOS “neurons” and an array of resistive-RAM (RRAM)-based “synapses,” which demonstrated STDP, a brain-like function.

TSMC keynoter suggests WLSI at IITC

Fri, 6 Jun 2013

In a keynote at the IEEE International Interconnect Technology Conference (IITC), Douglas Yu from TSMC talked about Moore’s Law scaling becoming increasingly difficult.

EVG and Dynaloy develop single-wafer cleaning solution

Mon, 6 Jun 2013

Single-wafer cleaning solution is suitable for 3D-IC/TSV, advanced packaging, MEMS and compound semiconductor applications.

"Generation Mobile": Advanced Packaging Technology at SEMICON West

Thu, 6 Jun 2013

Advanced packaging technology is undergoing dramatic changes as the smart phones and new sensor technologies demand continued improvements in form and function.

GLOBALFOUNDRIES introduces certified design flows for multi-die integration using 2.5D IC technology

Fri, 5 May 2013

The foundry plans to unveil a comprehensive set of certified design flows to support 2.5D IC product development with its most advanced manufacturing processes at next week’s 50th Design Automation Conference (DAC) in Austin, Texas.

Fab equipment spending: 23% growth for 2014

Tue, 6 Jun 2013

Fab equipment spending will grow two percent year-over-year  (US$ 32.5 billion) for 2013 and about 23 to 27 percent in 2014 ($41 billion) according to the May edition of the SEMI World Fab Forecast.

Leti to present latest R&D results in MEMS at Transducers’ 2013 in Barcelona

Wed, 5 May 2013

CEA-Leti will host a workshop for industrial companies to present its latest advances in MEMS and an overview of the success of its recent MEMS startup, Wavelens, during Transducers’ 2013 and Eurosensors XXVII in Barcelona, Spain.

Dow Corning and SÜSS MicroTec report new temporary bonding solution for 2.5D and 3D IC packaging

Wed, 5 May 2013

The semiconductor industry’s march toward broader 3D IC integration marked an important milestone this week at ECTC 2013, with the report of an advanced new temporary bonding solution for 3D TSV semiconductor packaging.

Mentor and Tezzaron optimize Calibre 3DSTACK for 2.5/3D-ICs

Mon, 5 May 2013

Mentor Graphics Corp. and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor Calibre 3DSTACK product into Tezzaron’s 3D-IC offerings.

Yole Developpement conducts 2.5D, 3DIC and TSV interconnect patent investigation

Wed, 5 May 2013

Yole Développement announced its 2.5D, 3DIC and TSV Interconnect Patent Investigation report. For this analysis of 3D packaging technology patents, more than 1800 patent families have been screened.

MOSIS collaborates with imec, Tyndall and ePIXfab on silicon photonics

Thu, 5 May 2013

MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has teamed up with imec, Ireland's Tyndall National Institute and ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs.

Amkor Technology appoints Steve Kelley president and CEO

Wed, 5 May 2013

Amkor Technology, Inc. today announced that Stephen D. Kelley has been appointed to serve as president and chief executive officer and as a director of the company, effective May 8, 2013.

Rudolph purchases assets from Tamar Technology

Mon, 4 Apr 2013

Rudolph Technologies, Inc. announced today that it has purchased selected assets, including a patent portfolio, relating to metrology capability from Tamar Technology, Newbury Park, Calif.

ESI acquires Semiconductor Systems business of GSI Group

Wed, 4 Apr 2013

 Electro Scientific Industries, Inc. today announced it had signed a definitive agreement to acquire the Semiconductor Systems business of GSI Group, Inc., a supplier of precision photonics, laser-based solutions and precision motion devices to the medical, industrial, scientific, and electronics markets

Global semiconductor sales outpace last year through Q1 of 2013

Tue, 5 May 2013

Sales in March 2013 were up slightly compared to February 2013 and March 2012.

2013: 450mm is the next big opportunity

Thu, 1 Jan 2013

In semiconductor manufacturing, 450mm is the next big opportunity. Issues of economic scale and complexity will force fab designers, OEMs and process integrators to investigate all open avenues in the search for solutions to the huge challenges that accompany 450mm.

2013: Continued strength in 200mm

Thu, 1 Jan 2013

80 percent of the devices used for portable and mobile applications are currently manufactured on 200mm or smaller wafers. How this plays out going forward could change who the dominant players will be.

2013: Accelerating R&D and decreasing time to yield

Thu, 1 Jan 2013

In order to maintain profitability manufacturers must increase the productivity and return from their R&D investments.

2013: Advanced packaging requirements are more complex, require new solutions

Wed, 1 Jan 2013

Advanced packaging requirements are driving the evolution of back end manufacturing to become more similar to the front end.

2013: Thriving in the transition to 450mm

Wed, 1 Jan 2013

The development of innovative technologies that solve the critical issues for the transition and adoption of 450-mm manufacturing will be the defining factor for whether a company merely survives or thrives.

2013: Building the internet of things with MEMS and 3D advances

Wed, 1 Jan 2013

It is becoming increasingly clear that new MEMS and 3D high-volume, low-cost manufacturing technologies will accelerate a radical change to society’s cyber skyline.

ISSCC 2013: Imagers, MEMS, medical and displays

Mon, 2 Feb 2013

Roland Thomas, subcommittee chair of ISSCC, writes of the substantial growth and future in key areas of technology.

Dow Corning and IBM scientists develop new materials for board-level photonics

Tue, 2 Feb 2013

Dow Corning and IBM scientists unveiled a major step in photonics yesterday at the Photonics West conference, using a new type of polymer material to transmit light instead of electrical signals within supercomputers and data centers.

Semiconductor R&D spending rises 7% despite weak market

Tue, 2 Feb 2013

Spending on research and development by semiconductor companies grew 7% in 2012 to a record-high $53.0 billion, even though the semiconductor market declined 1% to $317.6 billion.

STATS ChipPAC and UMC unveil 3D IC developed under open ecosystem

Wed, 1 Jan 2013

STATS ChipPAC and UMC announced the world's first demonstration of TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration.

Renesas and J-Devices sign MoU on transfer of back-end facilities

Wed, 1 Jan 2013

Renesas and J-Devices signed a memorandum of understanding regarding the transfer of the semiconductor back-end production business of three facilities operated by Renesas’ wholly owned manufacturing subsidiaries

Global 3D IC market report reveals major challenges

Mon, 2 Feb 2013

TechNavio's analysts forecast the global 3D IC market to grow at a CAGR of 19.7 percent over the period 2012-2016. However, the thermal conductivity issues could pose a challenge to the growth of this market.

ISSCC 2013: High-performance digital trends

Mon, 2 Feb 2013

Subcommittee chair Stefan Rusu of Intel in Santa Clara, CA will present on trends in high-performance digital. The relentless march of process technology, he says, brings more integration and performance.

IEDM 2012: The pivotal point for monolithic 3D ICs

Mon, 1 Jan 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc., blogs about the evolution of 3D technology seen at the International Electron Devices Meeting.  

Researchers create semiconductor 'nano-shish-kebabs' with potential for 3-D technologies

Wed, 2 Feb 2013

Researchers at North Carolina State University have developed a new type of nanoscale structure that resembles a “nano-shish-kebab,” consisting of multiple two-dimensional nanosheets that appear to be impaled upon a one-dimensional nanowire.

Flip-Chip expected to grow at a steady 9% pace, reaching $35 billion by 2018

Mon, 3 Mar 2013

Flip-Chip is big on value: in 2012, it was a $20B market, making it the biggest market in the middle-end area, and Yole Développement expects it to continue growing at a 9% clip, ultimately reaching $35 billion by 2018.

EV Group ships 300mm wafer bonding system to leading Chinese semiconductor foundry

Wed, 3 Mar 2013

Foundry to use wafers for 3D IC and advanced packaging volume production applications.

AGC and nMode launch subsidiary to develop advanced packaging technology

Tue, 3 Mar 2013

Tokyo-based Asahi Glass Co., Ltd. and nMode Solutions Inc. of Tucson, Arizona, have invested $2.1 million to co-found a subsidiary business, Triton Micro Technologies , to develop via-fill technology for interposers, enabling next-generation semiconductor packaging solutions using ultra-thin glass.

Blog: Dimensional scaling and the SRAM bit-cell

Thu, 3 Mar 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. and Benjamin S. Louie of Zeno Semiconductor blog about dimensional scaling as it relates to EUV and future per transistor device cost.

Silex and BroadPak partnership produces 2.5D IC packaging capabilities

Tue, 4 Apr 2013

Silex Microsystems and BroadPak today announced the immediate availability of their jointly developed silicon interposer solution in high-volume manufacturing.

FlipChip International and EZconn Czech a.s. announce partnership

Mon, 3 Mar 2013

FlipChip International (FCI), a developer of flip chip bumping, Wafer Level and embedded die packaging and EZconn Czech a.s. announced a partnership agreement today.

GLOBALFOUNDRIES demonstrates 3D TSV capabilities on 20nm technology

Tue, 4 Apr 2013

GLOBALFOUNDRIES today announced the accomplishment of a key milestone in its strategy to enable 3D stacking of chips for next-generation mobile and consumer applications.

RAM-memory-research-A-RAM-RERAM-MSDRAM-MELRAM projects

Wed, 10 Oct 2010

CNRS research on memory wafer fabWhile speculation abounds about what will be the next generation of memories and their applications, CNRS, a French government-funded research organization, has 4 new concepts of memories in 2010. The organization is actively recruiting collaborators on RE-RAM, A-RAM, MS-DRAM, and MELRAM memory technologies.

ConFab video: End user choices for 3D integration still unsettled

Thu, 5 May 2010

Tony Flaim, CTO at Brewer Science, describes the work the company is doing to enable 3D integration. While progress is moving forward, he tells SST's Debra Vogler that end users are still somewhat unsettled in their choices of manufacturing technologies.

Playing the field: Qualcomm embraces GlobalFoundries, reups with TSMC

Fri, 1 Jan 2010

Fabless giant Qualcomm has made two deals to reserve leading-edge semiconductor manufacturing capacity: one with longtime partner TSMC, and the other with upstart GlobalFoundries.

IEDM Reflections, Day 1: 2Xnm NAND, 3D integration, graphene FETs, biosensors

Wed, 12 Dec 2010

Techcet's Michael A. Fury reports in-depth from sessions at IEDM 2010, looking at papers on NAND flash using airgaps, a lock-and-key method for 3D integration, RF performance of graphene FETs, and FET-built DNA biosensors.


Wed, 12 Dec 2010

Tegal Corporation (Nasdaq: TGAL) is launching a new member of its ProNova family of high-density inductively coupled plasma (ICP) reactors for the company’s DRIE series wafer processing products. The ProNova2 is targeted for fast-growing 200mm MEMS and 3D IC applications.

Research updates on EUV, mask, cleaning, etc from Leti

Fri, 7 Jul 2010

In these three video interviews from SEMICON West 2010, Leti research directors speak with senior technical editor Debra Vogler. Yannick Le Tiec discusses cleaning; Michel Brillouet speaks on 3D packaging work, and Didier Louis updates us on advanced lithography.

Gary Smith EDA market statistics 2010: Summary

Thu, 7 Jul 2010

The biggest change in 2009 was Mentor passing Cadence to become number two in product sales in EDA. This is an indication of the market shift caused by the move into the ESL Methodology. Synopsys remains a strong number one.

CEA-Leti building 300mm R&D line dedicated to 3D integration applications

Tue, 7 Jul 2010

The integration line includes lithography, metallization, deep etching, dielectric deposition, wet etching and packaging tools.

A day at Albany CNSE: Leading-edge techs, innovation vs. efficiency

Tue, 10 Oct 2010

A daylong series of presentations, facility tour, and one-on-one discussions at a recent SEMI-hosted seminar at the U. of Albany College of Nanoscale Science and Engineering (CNSE) spurred intense discussion about the state of leading-edge chipmaking technologies, including 3D ICs and new device structures, and why Wall Street and roadmaps are hampering true technology innovation.

IMEC discusses major projects at SEMICON West

Thu, 8 Aug 2011

Ludo Deferm, IMEC, came to SEMICON West with several major announcements, from the system level to the layers of semiconductors. IMEC's major interests include scaling with 3D technologies, selective epitaxy, RRAM, lithography, and more.

SEMI comments on 450mm standards collaboration

Fri, 7 Jul 2011

Jonathan Davis, SEMI, chats about standards development in 450mm and 3D IC, as well as the importance of collaboration, and how it is happening at SEMICON West.

Customers, logic reshaping supplier collaboration landscape

Tue, 5 May 2011

Harvey Frye, vice-chairman of TEL America, summarized the new supplier landscape in his Confab talk, taking both a macro point of view of trends, and how his company as a top supplier is addressing them: collaboration among suppliers, and an increasing focus on consumer needs.

Imec brings new device architecture results to SEMICON West

Mon, 7 Jul 2011

At SEMICON West, imec is demonstrating a viable implant-free quantum-well (IF-QW) pFETs with an embedded silicon-germanium (SiGe) source/drain and 3D integration of a commercial DRAM chip on top of a logic IC.

2011 Best of West award finalists announced

Wed, 7 Jul 2011

Solid State Technology and SEMI today announced the finalists for the 2011

CEA-Leti Annual Review: The heart of Europe's semiconductor industry challenges

Tue, 6 Jun 2011

At CEA-Leti's Annual Review, Leti CEO Laurent Malier noted how the important role that research and technology organizations should play in strengthening industry in Europe, and how their roles differ from groups in other regions.

Historic semiconductor industry, SEMI moments from Stanley Myers

Wed, 7 Jul 2011

Stanley T. Myers talks what moments stand out for him as "historic" advances in semiconductor fab and the evolution of SEMI. He also shares advice for young engineers entering the semiconductor industry.

IEDM 2011: Hollow copper 3D TSVs

Mon, 11 Nov 2011

DAC seeks speakers bureau experts

Wed, 11 Nov 2011

The Design Automation Conference (DAC) is soliciting semiconductor industry experts for participation in invited sessions, panels, and other events at the 49th DAC, June 3-7, 2012 in San Francisco, CA.

SEMICON West 2012: Submit an abstract today

Mon, 12 Dec 2011

SEMI is looking for presenters for technical sessions and other opportunities at SEMICON West 2012, July 10-12 in San Francisco, CA.

imec's IEDM papers reach "record number"

Wed, 12 Dec 2011

imec is presenting a record number of 17 papers at the IEEE International Electron Device Meeting (IEDM), ending today in Washington, DC.

ASMC 2011: Rain doesn't damper the spirit

Tue, 5 May 2011

Intermolecular's John Behnke offers his impressions from Day 1 of this year's SEMI/IEEE Advanced Semiconductor Manufacturing Conference (ASMC) in New York. Highlights: a keynote from a suddenly famous GlobalFoundries exec, on-the-fly edge inspection, equipment health monitoring, and a TSV overview.

ASMC 2011: Approaching device scaling, manufacturing challenges with partnerships

Wed, 5 May 2011

Another eventful (but still rainy) day at this week's SEMI/IEEE Advanced Semiconductor Manufacturing Conference (May 16-18) offered two highlights sharing a theme: how partnerships can address challenges in device scaling and manufacturing.

Tessera focuses on semiconductor technologies beyond packaging

Thu, 4 Apr 2011

Tessera Technologies Inc. (Nasdaq:TSRA - News) began two corporate initiatives to expand its technologies in semiconductor microelectronics beyond packaging, and to potentially separate its Imaging & Optics business.

Pioneering new devices and materials for future ICs

Sun, 5 May 2011
It is expected that from the 15nm node on, the industry will need to adopt new transister architectures; among the contenders: FinFETs and TunnelFETs. Thomas Hoffmann, imec, Leuven, Belguim

Day 2, 3 talks on process integration, reliability, 3Di

Wed, 5 May 2011

John Iacoponi, IITC 2011 co-chair, reviews Day 2-3 discussions at IITC/MAM, including interconnect reliability, BEOL memory, 3D integration, process integration, ultralow-k, and future-looking talks on graphene and carbon nanotubes.

3D IC is only solution for scaling "up," says MonolithIC 3D exec

Thu, 3 Mar 2011

Transfer on top of processed wafer and replace gates (<400°C)Zvi Or-Bach, MonolithIC 3D, describes the TSV-beating monolithic IC fab process, and argues for scaling "up" rather than down. Or-Bach compares the costs of further semiconductor scaling to advanced packaging.

ASICs and FPGAs could take a lesson from autos, says Xilinx

Thu, 5 May 2011

Ivo Bolsens, Xilinx, compares crossover cars -- sports car performance with station wagon utility -- to semiconductor ASICs (high-performance) and FPGAs (flexible, easy to use, less NRE). The semiconductor industry needs a programmable platform that has ASICs' capabilities.

Imec ITF: The next wave of applications, with chips designed in 3D

Wed, 5 May 2011

In an SST-exclusive series of blogs, imec reports from its International Technology Forum this week in Brussels. Here, Jan Provoost looks at Pol Marchal's presentation on 3D integration and its impact on systems design -- and why sensors that smell are coming next.

SEMI says innovation is in, expensive differentiation is out

Mon, 5 May 2011

Tom Morrow, EVP, Emerging Markets Group/Chief Marketing Officer, speaks at ConFab 2011 about the semiconductor market's rebound from March 11's Japan earthquake, emerging markets like LEDs, and the trade organization's standards program for 3D ICs.

Trade-offs and infrastructure are keys to device scaling

Wed, 5 May 2011

Raj Jammy, VP of materials and emerging technologies at SEMATECH, covered a broad swath of CMOS scaling drivers, system and device trends, and infrastructure requirements.

Failure analysis challenges at 22nm turnkey FA tools

Tue, 1 Jan 2011

Paul Kirby, FEI, provides insights on the shift to complex 3D device structures and complex interconnect methods such as TSV. In the future, 3D analysis techniques could play increasingly important roles, he says. In advanced packaging, failure analysis is more critical because multi-die stacks can fail due to one bad die. This is an online exclusive essay in SST's Forecast for 2011: Back to Reality series.

ITRS 2010: What happened during this off-year?

Wed, 1 Jan 2011

The 2010 Update to the International Technology Roadmap for Semiconductors (ITRS), while not one of the scheduled major revisions, nevertheless includes substantial changes have occurred in 2010, including boosts in the timelines for NAND flash and DRAM device rollouts, backup plans for lithography forced by EUV delay, impending device and interconnect structural changes, and progress in 3D packaging.


Tue, 3 Mar 2011

Xradia microscope.Xradia has unveiled its latest micro computed tomography (CT) 3D X-ray imaging system, the VersaXRM. Kevin Fahey, PhD, VP of marketing at Xradia, discusses how the new platform uses geometrical magnification in tandem with an X-ray microscope.


Mon, 3 Mar 2011

Tabula will use the new capital to accelerate production of their 3PLD ABAX product family, expand customer and partner support infrastructures, and further next-generation product development in the rapidly growing programmable logic sector.


Thu, 3 Mar 2011

Applied Materials Inc. (AMAT) introduced the Applied Centura Conforma, with conformal plasma doping (CPD) targeted for 22nm and beyond logic and memory chips. The technology replaces ion beam implantation for conformal doping of complex 3D structures.

SEMATECH's Bryan Rice: Why it's time for a "refresh"

Tue, 10 Oct 2011

Bryan Rice, SEMATECH's newly appointed director of strategic initiatives, tells SST what his new job entails: what he sees as his biggest challenges, which areas will keep SEMATECH's main attention (hint: the "once and future king" of resources), and what new areas are being explored.

SEMICON Taiwan preview: Forums span key technology, markets

Tue, 8 Aug 2011

SEMICON Taiwan (Sept. 7-9) approaches, the island's most celebrated event for microelectronics manufacturing, coorganized by SEMI and the Taiwan External Trade Development Council (TAITRA), offers more than 60 programs and sessions and 550 exhibitors spanning the entire semiconductor value chain and related high-growth industries.

Inside Leti: FDSOI, 3D packaging, Si photonics work

Fri, 8 Aug 2011

Laurent Malier, CEO of Leti, described the research group's work and the outlook on fully depleted silicon on insulator (FDSOI), 3D packaging technologies, and integrated photonics on silicon.

Present at VLSI Technology and Circuits

Mon, 10 Oct 2011

The 2012 Symposia on VLSI Technology & Circuits, to be held in Hawaii, June 12-14 (Technology) and 13-15 (Circuits), will accept innovative, original work on microelectronics, ranging from gate stacks and advanced lithography to 3D packaging.

IDM economics at 32nm and beyond

Wed, 5 May 2008
by Ed Korczynski, senior technical editor, Solid State Technology
May 21, 2008 - Masaaki Kinugawa, GM of Toshiba's Oita operations, discussed the tough challenges faced by fabs developing advanced processes today in his Confab talk, including increasing complexity of process and device technologies (and proportionally rising costs) -- and an ugly truth waiting around the corner at the 32nm node.

Economics may drive push to 3D ICs, says SEMATECH's Arkalgud

Wed, 5 May 2008
by Bob Haavind, Editorial Director, Solid State Technology
May 21, 2008 - Beyond today's stacked chips in a package may come higher performance 3D stacked ICs using through-silicon vias to interconnect layers, according to Sitaram Arkalgud, who spoke on the economic implications of 3D at the ConFab in Las Vegas.

3D for microprocessors now...TSV later

Wed, 5 May 2008
by Ed Korczynski, senior technical editor, Solid State Technology
May 21, 2008 - While manufacturing of 3D ICs is today limited mostly to memory chip stacks and cell-phone camera modules, the next huge application seems to be the embedded memory in microprocessors. Subramanian Iyer, distinguished engineer and chief technologist of IBM's systems and technology group, explained the economic considerations behind 3D microprocessors at the ConFab in Las Vegas.

U. Albany's Denbeaux: EUV works, though far from what's needed

Tue, 3 Mar 2008
by Bob Haavind, Editorial Director, Solid State Technology
An insightful update on three key semiconductor technologies -- SOI, TSV/3D, and SOI -- sparked a lively Q&A following a SEMI-sponsored breakfast near Boston (Mar. 5). Here, Gregory Denbeaux, assistant professor of nanotechnology at the U. of Albany, gave an overview of progress needed in EUV to make it suitable for high volume manufacturing.

SEMATECH's Arkalgud: A 3D/TSV route to higher IC densities

Tue, 3 Mar 2008
by Bob Haavind, Editorial Director, Solid State Technology
An insightful update on three key semiconductor technologies -- SOI, TSV/3D, and SOI -- sparked a lively Q&A following a SEMI-sponsored breakfast near Boston (Mar. 5). Here, Sitaram Arkalgud, head of SEMATECH's 3D interconnect program in Albany, discusses the expected evolution of through-silicon vias (TSVs) and 3D chip stacks for future electronics.

IBM's Starkey: The case for SOI won't diminish w/ shrink

Tue, 3 Mar 2008
by Bob Haavind, Editorial Director, Solid State Technology
An insightful update on three key semiconductor technologies -- SOI, TSV/3D, and SOI -- sparked a lively Q&A following a SEMI-sponsored breakfast near Boston (Mar. 5), held at an MKS Instruments facility. Here, Gordon Starkey, a senior engineer in technical operations for IBM, explained how silicon-on-insulator (SOI) has made a transition from a niche to mainstream technology.

Tracking the future of TSV

Thu, 2 Feb 2008
by Ed Korczynski, Senior Technical Editor, Solid State Technology
A new report from TechSearch International forecasts millions of silicon wafers will be made with through-silicon vias (TSV) in the year 2014. With TSV technology now moving past the feasibility (R&D) phase and into the commercialization phase, the question isn't whether this 3D interconnect will be adopted, but how soon it will balance cost/performance vs. existing technologies to break into real mainstream use.

Ziptronix joins low-cost quest for true 3D-IC

Wed, 10 Oct 2008
Ziptronix execs reveal technical details on its direct bond interconnect technology, which the company says is key to low-cost wafer-to-wafer or chip-to-wafer bonding without high-temperature compression.

Suss swaps CEO over "differing" strategic views

Tue, 10 Oct 2008
Suss MicroTec has replaced board member and CEO Stefan Schneidewind with Christian Schubert effective immediately, citing "differing views regarding the future strategy of the company." A search for a new permanent CEO will take place.

Tegal+AMMS eyes growth in 3D packaging, MEMS

Mon, 9 Sep 2008
Tegal Corp.'s proposed acquisition of Alcatel Micro Machining Systems' (AMMS) deep reactive ion etch (DRIE) and plasma-enhanced chemical vapor deposition (PECVD) products is "a critical part of our growth strategy" to extend into higher-growth markets in 3D IC packaging and MEMS devices, the company asserts.

IMEC research energetically stacks up

Mon, 10 Oct 2008
Advanced Packaging's Gail Flower reports from presentations at IMEC's recent annual research review, centering on two areas of predicted high growth: 3D stacked ICs including through-silicon vias (TSV), and crystalline Si and organic solar cells.

IMEC, Qualcomm pushing 3D integration

Mon, 7 Jul 2008
July 14, 2008 - Wireless fabless developer Qualcomm has joined European R&D consortium IMEC's industrial affiliation program on 3D integration to understand and develop ways to use 3D wafer-level packaging and 3D stacked ICs in future wireless products.

IMEC: Fabless/fab-lite trend requires extended R&D model

Tue, 7 Jul 2008
In a pre-SEMICON West interview, Ludo Deferm, IMEC's VP of business development, discusses the changes required in R&D models to accommodate fabless/fab-lite companies, and how IMEC is helping research partners understand the impact of 3D technology and the added value of design.

AMAT accelerating TSV implementation, launches Silvia etch tool

Mon, 12 Dec 2008
Sizing up a TSV market beyond the early adopters, Applied Materials is collaborating with material and equipment suppliers (and others) to ensure the full readiness of TSV implementation. AMAT execs update SST on the firm's TSV efforts, including a new TSV process sequence developed with Semitool and a new etch tool.

Tegal seeks "DRIE" land in MEMS

Tue, 9 Sep 2008
Tom Mika, CEO of Tegal, gives SST some further insights into his company's plans behind its proposed acquisition of Alcatel Micro Machining Systems' deep reactive ion etch and other technologies -- including how the company will leverage its existing presence in MEMS, finding the balance between serving R&D and production needs, and fighting much larger competitors.

IMEC's 3D efforts: New higher-AR TSVs for thicker dies

Tue, 8 Aug 2009
Bart Swinnen, director of interconnect and packaging in IMEC's process technology unit, discusses the status of 3D technology efforts -- in particular, IMEC's work on TSV tech that will enable higher aspect ratio TSVs suitable for thicker dies.

Luc Van den hove helms IMEC, discusses strategy

Tue, 6 Jun 2009
Amid preparations for IMEC's 25th anniversary celebration, SST spoke with Luc Van den hove, now president/CEO of European R&D consortium IMEC, who discussed the research center's strategy and the keys to its success over the years.

Alchimer's new TSV process: When less really is more

Mon, 6 Jun 2009
Alchimer CEO Steve Lerner tells SST how its improved eG ViaCoat wet deposition process of copper seed metallization of through-silicon vias (TSV) can now be used on existing dry equipment -- and provides reliability test results.

NEC: Trumping conventional scaling with 3D packaging

Mon, 2 Feb 2009
In a bid to expand applications for 3D packaging, NEC has developed a 3D chip-stacked flexible memory to support large-scale high-performance systems-on-chip (SoC).

EVGroup: Ready for whatever comes with 3D integration

Wed, 8 Aug 2009
Steven Dwyer, VP & GM, North America at EV Group, provides highlights of 3D integration papers the company presented at SEMICON West. By achieving alignment accuracy down to 200nm, thin wafer handling at thicknesses <10μm, and 300mm-capable wafer bonding, he says the company is ready for whatever comes along.

SEMATECH's 3D work in Albany

Wed, 8 Aug 2009
Larry Smith, sr. member of the technical staff in SEMATECH's 3D interconnect division, discusses toolset acquisitions at the U. of Albany's CNSE, where work focuses on replacing traditional global interconnect and intermediate level processes.

Behind Brewer Science's wafer bonding work

Mon, 8 Aug 2009
Karen Twillmann, executive director of corporate marketing at Brewer Science, and Dan Wallace, the company's director of 3D packaging, discusses the advances made by the company's temporary bond adhesive for wafer bond applications.

Memory sector upended, driven by 3D packaging tech, says Yole

Fri, 5 May 2009
New integration trends and disruptive packaging technologies, notably 3D TSVs, will cause major technical changes in the memory semiconductor sector, but ultimately pave the way for future growth, according to a recent report from Yole Développement.

ITRI adds AMAT tools for 3D IC work

Fri, 10 Oct 2009

Taiwan's Industrial Technology Research Institute (ITRI) will add Applied Materials to its partners for developing 3D chip stacking technology, by placing "a full line" of AMAT processing tools in its labs.

How CMP enables innovation in memory, 3D, MEMS

Wed, 8 Aug 2009
Robert Rhoades, CTO, Entrepix, describes the nontraditional technology behind TFT-dual gate memory and how CMP enables that innovation among others -- e.g., TSVs, 3D packaging, MEMS, and engineered substrates.

EVG, AMAT pair for 3D thin-wafer bonding

Fri, 7 Jul 2009
EV Group and Applied Materials say they will jointly develop wafer bonding processes for making through-silicon vias (TSV) in 3D IC packaging applications, working as members within the Semiconductor 3D Equipment and Materials Consortium (EMC-3D).

Applying TCAD sim to PV, 3D TSVs

Thu, 7 Jul 2009
Ric Borges of Synopsys discusses the application of TCAD simulation to multijunction and CPV solar cells.

Future bright for 3D consortium

Wed, 7 Jul 2009
Paul Siblerud of Semitool discusses 3D integration challenges and announces the latest news from the EMC-3D Consortium.

Stepping up to the 3D challenge

Wed, 7 Jul 2009
Soitec's president and CEO, André-Jacques Auberton-Hervé, discusses the three pillars of 3D integration at the wafer level, as well as bonding at room temperature. Also noted is Soitec's partnership with IBM, announced during SEMICON West.

3D integration: A status report

Tue, 7 Jul 2009
3D IC technology, an alternative approach to wire-bonded chip stacking utilizing interconnets with through-silicon vias (TSVs) fabricated with front-end-like processes, is a hot topic at SEMICON West, and the focus of an on-line virtual forum hosted by public relations firm MCA.

ICOS, IMEC to develop 3D packaging metrology

Thu, 7 Jul 2006
July 27, 2006 - ICOS Vision Systems Corp. NV and European R&D center IMEC have agreed to collaborate on development of metrology methods targeting 3D packaging processes for ICs, including wafer-level packaging, flip-chip, systems-in-package, and microelectromechanical systems (MEMS).

Cookson, Microbonds combine insulated wire bonding, mold compounds

Thu, 7 Jul 2006
July 6, 2006 - Cookson Electronics Semiconductor Products and Microbonds Inc. have formed a codevelopment project to combine Microbonds' X-Wire insulated wire bonding technology with Cookson's Plaskon family of mold compounds.

SanDisk widens memory reach with Msystems deal

Mon, 7 Jul 2006
July 31, 2006 - In the latest big move to consolidate power in the memory sector, flash memory giant SanDisk Corp., Milpitas, CA, has agreed to acquire Msystems Ltd., Kfar Saba, Israel, in an all-stock deal valued at up to $1.55 billion, including stock options and convertible debt.

Samsung touts 3D methods, multilayered dielectric in new 50nm DRAM chip

Thu, 10 Oct 2006
October 19, 2006 - Samsung Electronics Co. Ltd. says it has developed a 50nm DDR2 DRAM chip utilizing 3D design and multilayered dielectrics, a process that enhances performance and data storage capabilities.

Consortium to develop cost-effective 3D interconnects

Thu, 10 Oct 2006
October 12, 2006 - A list of equipment providers, materials companies, and researchers have joined to create an international consortium to address technical and cost issues of creating of thru-silicon-via (TSV) 3D chip interconnect, for use in chip stacking and MEMS/sensor packaging.

FlipChip, Engent to make 3D packaging tech

Fri, 5 May 2006
May 26, 2006 - FlipChip International LLC and Engent Inc. are partnering to develop 3D wafer-level CSP (WLCSP) technologies, seen as a low-cost alternative to system-on-chip for highly integrated stacked die packaging applications.

STATS ChipPAC handing low-end packaging ops to China firm

Mon, 6 Jun 2006
June 26, 2006 - STATS ChipPAC Ltd., a provider of semiconductor test and packaging services, has signed a deal with China Resources Logic Ltd. to set up a JV in Wuxi, China, providing assembly and test service for STATS' lower-end leadframe package families, allowing the firm to focus on more leading-edge products such as system-in-package, flip-chip, and 3D technologies.

SEMATECH 3D project seeks interconnect answers

Thu, 2 Feb 2006
February 9, 2006 - SEMATECH has launched a new project to explore the feasibility of three-dimensional (3D) interconnect technology for the semiconductor industry.

IBM tips TSV 3D chip stacking technique

Fri, 4 Apr 2007
April 13, 2007 - IBM says it has developed a way to incorporate through-silicon vias (TSV) into its chipmaking process that shortens data-travel distances by up to 1000x and allows for 100x more pathways than 2D chips. Samples of 65nm chips using the 3D stacking technique will be shipped by year's end, with production ramping in 2008.

Ziptronix 3D interconnect tech targets multilayer CMOS ICs

Thu, 4 Apr 2007
April 5, 2007 - Ziptronix Inc. and Raytheon Vision Systems (RVS) say they have demonstrated compatibility of Ziptronix's "direct bond interconnect" (DBI) interconnect technology with multilayer CMOS IC processes, involving 3D integration of five-layer metal 0.5-micron CMOS devices with silicon PIN detector devices.

IMEC looks to the future as SEMICON West opens

Tue, 7 Jul 2007
As another SEMICON West opens, IMEC's experts discussed with WaferNEWS what they see are they major keys to the future of semiconductor industry: exploring new markets, bringing finFETs into manufacturing, mastering 3D integration, and addressing sub-32nm low-k deposition challenges.

CEA/Leti, Alcatel forge DRIE pact for 3D interconnects

Thu, 7 Jul 2007
July 18, 2007

IMEC extends 3D system integration program

Wed, 7 Jul 2007
July 18, 2007 - IMEC has expanded its 3D packaging research program to fully exploit the potential of novel 3D technologies. Besides 3D interconnection technologies developments, the program is extended with research on system design methodologies. Both the technology and design sub-programs will be based on actual system requirements and closely coupled.

Amkor, IMEC sign agreement for 3D WLP

Wed, 7 Jul 2007
July 18, 2007 - At SEMICON West, Amkor Technology Inc., a provider of advanced semiconductor assembly and test services, and IMEC, the independent nanoelectronics and nanotechnology research center based in Belgium, announced that they have entered into a 2-year collaboration agreement. They will develop cost-effective, 3D integration technology based on wafer-level processing techniques.

Qimonda's Arkalgud to head up SEMATECH's 3D program

Fri, 1 Jan 2007
January 5, 2007 - SEMATECH has appointed Sitaram Arkalgud, appointee from Qimonda/Infineon Technologies, as director of its new 3D interconnect initiative, in addition to his duties leading SEMATECH's interconnect division.

Manufacturing alliances: An expanded role for equipment suppliers

Mon, 5 May 2007
In the new consumer-driven electronics industry, where beating your competition to market with innovative technology is the surest route to success, process control equipment suppliers have an expanded role in manufacturing alliances to help dramatically shorten product-development and production-ramp times, and thus significantly improve yield and profitability, according to Brian Trafas, chief marketing officer at KLA-Tencor, in his talk at the Confab in Las Vegas.

Alcatel, Tronics join for MEMS DRIE

Thu, 6 Jun 2007
June 7, 2007 - Tronics Microsystems SA and Alcatel Micro Machining Systems (AMMS) say they will jointly develop deep reactive ion etch (DRIE) systems for "extreme-performance" MEMS.

June 2007 Exclusive Feature 2: 3D INTERCONNECTS
IITC PREVIEW: Are 3D interconnects ready for prime time?

Fri, 6 Jun 2007
By Phil LoPiccolo, Editor-in-Chief

Among the most significant developments in interconnect slated to appear at this month's International Interconnect Technology Conference (IITC, June 4-6, in Burlingame, CA) involve 3D chip architectures. Sitaram Arkalgud, director of SEMATECH's interconnect division and its newly created 3D interconnect initiative, calls 3D chip architecture his "new religion," because stacked chips allow interconnects to be much shorter than...

STATS ChipPAC readies R&D site in Singapore

Mon, 5 May 2007
May 14, 2007 - STATS ChipPAC has formally established its new R&D facility in Singapore, to develop next-generation technologies including through-silicon vias (TSV), microbump bonding methods for 3D die, silicon substrate-based system-in-package solutions, and embedded active die technology.

STATS ChipPAC offloading more lines to China

Mon, 6 Jun 2007
June 11, 2007 - STATS ChipPAC Ltd. says it will sell certain assembly and test assets for its discrete power packages to China's Ningbo Mingxin Microelectronics Co. Ltd., following a similar transaction a year ago to farm out some work to mainland China in order to pursue better growth opportunities in areas such as system-in-package, flip-chip, and 3D technologies.

PACKAGING BEAT: Industry leaders vie for memory-stacking bragging rights

Tue, 6 Jun 2007
Samsung, Hynix, and Akita Elpida have all made announcements recently about their latest achievements in memory stacking technology. There was definitely a competitive tone to these releases, but they actually appear to be pushing somewhat different agendas.

Tezzaron, Chartered working on 2D "iRAM" hybrid, 3D ICs to come

Tue, 6 Jun 2007
June 12, 2007 - Tezzaron Semiconductor says it is ramping its 2D "3T-iRAM" line of 72Mbit memory devices at Singapore foundry Chartered Semiconductor on the foundry's 0.13-micron process technology, and plans to use this SRAM drop-in replacement as the basis for its first 3D ICs. Robert Patti, Tezzaron CTO, discusses both technologies with WaferNEWS.

IITC PREVIEW: Are 3D interconnects ready for prime time?

Tue, 5 May 2007
Among the most significant developments in interconnect to look for at the upcoming International Interconnect Technology Conference (IITC, June 4-6, in Burlingame, CA) are those involving 3D chip architectures. Sitaram Arkalgud, director of SEMATECH's interconnect division, discusses the "new religion" of 3D chip architecture with WaferNEWS, and explains why it's the most promising route to eliminating the main stumbling block to higher chip speeds and lower power consumption.

Elpida joins IMEC's CMOS research platform

Wed, 3 Mar 2007
March 14, 2007 - Elpida Memory Inc., a Japanese supplier of dynamic random access memory (DRAM), has entered into a multi-year partnership with IMEC, an independent nanoelectronics research center, to perform R&D for beyond 50nm DRAM process generations, said IMEC today.

Moore's Law to head z-ward?

Mon, 10 Oct 2007
While the industry struggles to continue on the Moore's Law track, 3D approaches superior to those of systems-on-chip may provide an interim solution if the shrink slows down. A SEMATECH-organized workshop in Albany, NY earlier this month (Oct. 11-12) addressed fundamental issues about 3D, including four reasons why every chipmaker has 3D/TSVapproaches on its roadmap, and what needs to be solved before 3D can be effective beyond simple memory.

EV Group, Brewer demo ultrathin wafer bonding platform

Wed, 12 Dec 2007
December 5, 2007 - EV Group (EVG) and Brewer Science say they have demonstrated temporary wafer bonding capabilities for a wide range of backside processes, including through-silicon vias (TSVs) and backside metallization, using an approach optimized for high-temperature advanced packaging applications.

STATS ChipPAC expanding flip-chip services in China

Tue, 11 Nov 2007
November 20, 2007 - STATS ChipPAC says it will expand its flip-chip offerings to its Shanghai, China operation, encompassing wafer bump, sort, assembly and final test. Volume production is expected to start in 1H08, followed by a second phase adding electroplated wafer bumping capabilities for 200mm wafers in 1H07 and 300mm wafers in 2H08.

Trio creates Dresden center under "Nanoanalysis" R&D project

Tue, 11 Nov 2007
November 6, 2007 - AMD, Carl Zeiss SMT, and Qimonda AG are forming a 12M euro (US ~$17.4M) "innovation center" in Dresden, Germany ("Silicon Saxony"), under a larger "Nanoanalysis" project to develop new analytical and characterization methods for next-gen chip development.

Ziptronix reports first 3D SoC

Mon, 9 Sep 2005
September 26, 2005 - Ziptronix, Morrisville, NC, has made good on its efforts at creating a three-dimensional IC device to serve as an alternative to system-in-package (SiP) technology, according to a company statement.

Ziptronix appoints Phil Nyborg as new CEO

Wed, 3 Mar 2005
March 2, 2005 - Ziptronix has appointed 17-year semiconductor industry veteran Phil Nyborg as its new president and CEO. The company said that Nyborg will guide it as it more fully commercializes its proprietary bonding and interconnect processes for 3DICs.

RSL opens packaging R&D lab with Suss MicroTec

Wed, 8 Aug 2005
August 10, 2005 - RoseStreet Labs (RSL), Phoenix, AZ, has announced the opening of its 3D Research and Development laboratory for next-generation semiconductor packaging, as well as an alliance with Suss MicroTec, which will provide the lab with a full suite of lithography and 3D packaging equipment.

Amkor to expand development of 3D IC packages

Thu, 4 Apr 2001
April 5, 2001 - West Chester, PA - Amkor Technology is expanding its development and qualification of 3D IC packages in order to reduce production costs and handling time. 3D or stacked ICs also require less space, have higher reliability and better electrical performance than the combination of devices they replace, the company said.

3D Packaging — Which Way to Go?

Mon, 1 Jan 2008
adapted for print by AP editors

This article, the first in a series of three on 3D packaging technology, summarizes information presented during a November 2007 webcast produced by Advanced Packaging magazine. Participants were Jean-Christophe "J.C." Eloy, founder and GM of Yole D

Electromechanical Coating Processes

Fri, 5 May 2008
eG ViaCoat is the latest in Alchimer's eGTM series of electrochemical coating processes, for the metallization of high aspect ratio through-silicon vias (TSVs) used in advanced 3D packaging applications. It reportedly produces conformal, thin, uniform, and adherent copper seed layers, even on resistive barriers. It is said to enables significant reductions in cost of ownership (CoO) compared to dry vacuum processes.

3D Interconnection Cube

Fri, 12 Dec 2008
The 3D interconnection chip carrier from Microcertec S.A.S 3-D combines precision-grinding of ceramics with thin-film metallization and laser micromachining to create a 3D package option for chips and ICs.

Datacon Technology Joins EMC-3D Consortium

Wed, 4 Apr 2008
(April 9, 2008) Radfeld, AUSTRIA — EMC3D, an international semiconductor equipment and materials consortium dedicated to the cost-effective development of 3D through silicon via (TSV) interconnects, announced the addition of Datacon Technology to the organization. Datacon, manufacturer of die bonding & sorting equipment will provide high-precision assembly expertise to the consortium.

BiTS Workshop: A Success Story

Mon, 4 Apr 2008
By Gail Flower, editor-in-chief
The ninth annual Burn-in and Test Socket Workshop (BiTS 2008) on March 9-12, 2008 in Mesa, AZ, presented an interactive, growing, and technical successful forum for experts dedicated to sharing knowledge. BiTS brought together 350 conference attendees and 60 exhibitors worldwide from users of sockets, boards, burn-in systems, handlers, packaging engineers, and suppliers to the industry.

3D Packaging Technologies Expected to Dominate Industry

Wed, 4 Apr 2008
(April 23, 2008) Palo Alto, CA— 3D packaging is expected to emerge as a dominant performing solution in the electronic/chip packaging industry. Its performance promises to drive efforts across the entire supply chain to successfully deploy it, according to analysis reports from Frost & Sullivan's Global Trends in Electronic/Chip Packaging. Analysis indicates that the industry is moving beyond system on chip (SoC) to explore various forms of system in package (SiP).

New Study Forecasts Realistic 3D TSV Market

Wed, 2 Feb 2008
(February 13, 2008) Austin, TX — A new study reports that 3D through-silicon vias (TSV) will eventually be adopted, but the timing for mass production depends on how the cost of the new technology compares with that of existing technologies. Design, thermal, and test issues remain a barrier to TSV adoption in some applications, although progress is being made.

Cost Analysis Tool for 3D IC Manufacturing

Mon, 3 Mar 2008
This intuitive cost-of-ownership (CoO) tool model is specifically designed to evaluate the cost of a given through-silicon-via (TSV) process flow. It has been developed using Excel so as to be widely exploitable and upgradable. This CoO tool will enable evaluation of the cost/wafer level for manufacturing TSVs using user inputs or pre-defined parameters.

IEEE International Interconnect Technology Conference Goes 3D

Tue, 5 May 2008
(May 7, 2008) Burlingame, CA — When the IEEE International Interconnect Technology Conference convenes at the Hyatt Regency San Francisco Airport Hotel, Burlingame, CA, June 1-4, the focus will be squarely on 3D technologies. Attendees will have the opportunity to gain both fundamental knowledge and practical manufacturing advice from 3D experts at chip companies and universities from around the world.

SMTA's 3D/SiP Symposium Promotes Industry-wide Collaboration

Tue, 5 May 2008
Last week's 3D/SiP Symposium hosted by SMTA, and co-sponsored by Advanced Packaging magazine, turned out to be an intimate gathering of approximately 55 attendees representing not only the U.S., but Canada, France, Japan, Taiwan, United Kingdom, Austria and the Republic of Korea.

Oerlikon Esec Introduces Product Family at SEMICON Singapore

Mon, 5 May 2008
(May 5, 2008) Cham, Switzerland and Singapore — Oerlikon Esec, provider of automated chip assembly equipment and system solutions for the semiconductor industry, formally introduced the introductory platform of an entirely new product family at an official unveiling during SEMICON Singapore. The Die Bonder 2100 xP targets the high-volume epoxy die attach market.

EV Group Expands Presence in Korea

Wed, 5 May 2008
(May 14, 2008) St. Florian, AUSTRIA — EV Group, equipment manufacturer for semiconductor, MEMS, and nanotechnology applications, announced the opening of a subsidiary, EV Group Korea Ltd., in Seoul, Korea to serve as a direct-to-customer site for sales, service, and support efforts for EVG's existing and potential new customer base. The subsidiary will reportedly house sales, service, process/application and administrative capabilities.

3D Integration Tour: Are TSVs the Future of Advanced Packaging?

Thu, 5 May 2008
By Julia Goldstein, contributing editor
(May 22, 2008) San Jose, CA — The "3D Integration North American Tour" came to San Jose on May 15 after stops in Durham, NC and Dallas, TX. The event, hosted by SUSS MicroTec, Surface Technology Systems (STS) and NEXX Systems outlined the current state of the art in through silicon vias (TSVs) and related technology.

Two Routes to TSV Emerging

Fri, 7 Jul 2007
By Bob Haavind, editorial director, Solid State Technology

3D chip packaging with through-silicon vias (TSVs) will transform the industry over the next 3–5 years, say presentations and discussions at SEMICON West. Using TSVs could enable compact packaging with increased performance. Two approaches to TSV are leading the evolution.

3D Conference Looks at Successful Integration Routes

Tue, 12 Dec 2008
By Gail Flower, editor-in-chief
(December, 2, 2008) BURLINGAME, CA — On November 17

3D Packaging — How to Build 3D Packages from Design through Materials & Equipment

Mon, 2 Feb 2008
adapted for print by AP editors

This article is the second in a series on 3D packaging technology, and summarizes information presented during a December 2007 webcast produced and hosted by Advanced Packaging magazine. Participants included: Dan Schmauch and Rozalia Beica, Semitool Inc.; Jean-Marc Thevenoud, Alcatel MicroMachining Systems; and Markus Wimplinger, EV Group.

The Trouble with News

Thu, 5 May 2008
You would think that because I’m a National Public Radio junkie, news would be of vital importance to me – any type of news.

It’s About Time

Tue, 7 Jul 2008
What do you do when work doesn’t leave a moment to spare? You take a break to gain a new perspective.

Enabling Cooling Strategies for 3D packages

Tue, 7 Jul 2008
Riding on recent advances in nano-fabrication technology, thin-film thermoelectric coolers (TF-TEC) have been developed with active material as thin as 10-20

Designing Modern 3D Packages with Mixed Technology Content

Tue, 1 Jan 2008
Packaging technology has evolved over the years, transitioning into more of a revolution with the introduction of new packaging styles practically every month. Designers face designing extremely high-performance packages with mixed technology content such as high speed digital, analog, and RF.

iNEMI Takes Roadmap Workshop to Asia

Mon, 5 May 2006
Herndon, VA — The International Electronics Manufacturing Initiative (iNEMI) will hold a 2007 Roadmap workshop in Shanghai, China, in tandem with the High-density Microsystem Design and Packaging and Component Failure Analysis in Electronics Manufacturing (HDP) 2006 conference. The half-day workshop will take place June 27, 2006, on the Yan Chang Campus of Shanghai University.

Package-on-Package Trends and Technology

Sat, 7 Jul 2006
Destined for Growth

Actel Delivers 4x4 mm Package for FPGAs

Wed, 11 Nov 2007
(November 14, 2007) MOUNTAIN VIEW, CA — Actel Corp. has announced it is offering its low-power 5mW IGLOO field-programmable gate arrays (FPGAs) in a 4-mm package with a 0.4-mm ball pitch, reportedly the smallest package for any programmable logic device on the market.

Fred Roozeboom, Ph.D., of NXP Joins EMC3D Consortium as Technical Advisor

Wed, 11 Nov 2007
(November 14, 2007) EINDHOVEN, The Netherlands — Fred Roozeboom, Ph.D., research fellow at NXP Semiconductors Research and a professor at the Eindhoven University of Technology, has agreed to join the EMC3D consortium and provide technical advice and guidance in support of the EMC3D effort to quickly bring the technology of through-silicon via (TSV) chip stacking to market.

SEMICON Europa: An Editor's Perspective

Tue, 10 Oct 2007
For an editor of a semiconductor manufacturing publication, there are several sides to every trade show. On one hand are the technical sessions, where we get a glimpse of the latest and greatest technologies being developed. On the other hand, are the industry players

3D Integration: Preparing a Brilliant Future

Fri, 11 Nov 2007
By Rudi Cartuyvels, IMEC

3D integration explores the possibilities to interconnect active devices in different 2D planes. These interconnects can be considered at different levels of the wiring hierarchy, from the package, over global, to local interconnect levels. The future looks bright for 3D integration, as it promises to become a Holy Grail for system integration with uses in electronics, consumer, automotive, medical, office, and networking applications.

Agilent Technologies and Multiprobe to Expand Partnership

Tue, 12 Dec 2007
(December 4, 2007) SANTA CLARA, CA — Agilent Technologies Inc. and Multiprobe Inc. today announced their intent to expand the companies' strategic partnership. As a result, Agilent will sell and support Multiprobe's Multiscan atomic force prober (AFP) to customers in Asia and Japan.


Fri, 3 Mar 2003
The following companies will be exhibiting these products at APEX 2003, taking place Monday, March 31 through Wednesday, April 2 in Anaheim, Calif. Be sure to visit them to see their latest innovations, and pick up SMT's official Show Daily for more product coverage. ( March 28)
Click here for these and more product briefs.

STMicroelectronics uses TSV in high-volume MEMS devices

Tue, 10 Oct 2011

STMicroelectronics (NYSE:STM) has implemented through-silicon vias (TSV) in high-volume micro electro mechanical system (MEMS) devices. ST is using TSV in its smart sensors and multi-axis inertial modules.

Silex MEMS TSV tech licensed to Nanoshift

Wed, 11 Nov 2011

Silex Microsystems licensed its Silex Sil-Via through-silicon-via (TSV) packaging platform to Nanoshift for use in early development of complex MEMS products.

MEMS alternatives for miniature auto-focus cameras

Wed, 11 Nov 2011

Dr. Giles Humpston, Tessera, presents the free, on-demand webcast Lens Tilt in Small Auto-Focus Cameras. Dr. Humpston covers the dominant auto-focus miniature camera technology today -- VCM -- and an improved technology based on MEMS, which is being commercialized now.

Lam Research ships first 300 mm system for 3-D IC through-silicon via etch

Wed, 8 Aug 2007
Lam Research Corp. has shipped its first 300 mm 2300 Syndion etch system, designed for 3-D IC through-silicon via (TSV) etch applications.

Amkor, IMEC collaborate on 3D wafer-level packaging

Thu, 7 Jul 2007
Amkor, IMEC collaborate on 3D wafer-level packaging

RoseStreet opens new lab with Suss tools

Thu, 8 Aug 2005

Panasonic invests in Alchimer deposition tech for TSVs

Mon, 7 Jul 2010

Alchimer S.A., a provider of nanometric deposition technology for through-silicon vias (TSV), semiconductor interconnects, and other electronic applications, announced that Panasonic Corporation (NYSE: PC) has become an equity investor in the company.

Toshiba tips Si nanowires for 16nm chips

Thu, 6 Jun 2010

Presenting at the VLSI Symposium, Toshiba says it has developed a silicon nanowire transistor with vastly improved on-current levels, targeting 16nm and beyond system LSIs.

SEMATECH acquires etch system from Tokyo Electron

Thu, 10 Oct 2008
October 30, 2008: SEMATECH and the College of Nanoscale Science and Engineering (CNSE) at the U. at Albany will use TEL's Telius SP UD system in a 300mm 3D R&D center.

Tracit's circuit layer transfer tech enables e2v's next-gen image sensors

Thu, 5 May 2007
e2v, developer and manufacturer of electronic components and subsystems, has announced a new generation of high-sensitivity imaging sensors that leverage technology from Tracit Technologies, a new division of the Soitec Group.

NEXX Systems to participate in IMEC's Industrial Affiliation Program on 3D integration

Wed, 6 Jun 2008
June 18, 2008 -- NEXX Systems, a provider of process equipment for advanced wafer-level packaging applications, will participate in IMEC's Industrial Affiliation Program (IIAP) on 3D integration.

Tohoku University and imec partner to advance research

Mon, 6 Jun 2012

Tohoku University of Sendai, Japan and imec signed a collaboration agreement during the Belgian economic mission to Japan, expanding their R&D into areas such as MRAM and 3D semiconductor packaging.

X-Fab takes majority stake in MFI, widens MEMS portfolio to support growth push

Thu, 11 Nov 2012

X-Fab Silicon Foundries says it has become the majority shareholder in German MEMS Foundry Itzehoe GmbH (MFI), the latest in a series of recent moves to raise its profile as a top MEMS foundry.

GlobalFoundries to fab Sand 9's MEMS timing products

Tue, 10 Oct 2012

Sand 9 is partnering with GlobalFoundries for high-volume manufacturing of its microelectromechanical systems (MEMS) timing technology, which incorporates silicon-on-insulator (SOI) and through-silicon vias (TSV).

Silex devs wafer-level MEMS fab technologies for mobile devices

Mon, 1 Jan 2012

Silex Microsystems joined Energy-efficient Piezo-MEMS Tunable RF Front-End Antenna Systems for Mobile Devices to develop TSVs, PZT thin films, and other technologies for high-performance RF systems targeting mobile devices.

Nextreme brings thin-film on-par with bulk thermoelectrics

Mon, 2 Feb 2012

Nextreme Thermal Solutions announced that its thin-film thermoelectric technology has achieved a 60.1°C temperature difference between its cold and hot sides at an ambient temperature of 24.7°C, bringing it on par with the performance of bulk thermoelectric technology.

Applied Materials leads TSV drive for 3D ICs

Mon, 12 Dec 2008
December 1, 2008: Applied Materials Inc. says it is leading a major effort to enable the widespread adoption of through-silicon vias (TSVs) for vertically stacking integrated circuits (ICs) to boost chip performance and functionality, working internally and with other equipment suppliers to develop an integrated, high-performance on-wafer process flow to lower costs, reduce risk, and accelerate time-to-market for customers.

Inside the Hybrid Memory Cube

Wed, 9 Sep 2013
The HMC provides a breakthrough solution that delivers unmatched performance with the utmost reliability.

Ultraviolet light to the extreme

Wed, 10 Oct 2013
For the first time, researchers have mapped this EUV emission and developed a theoretical model that explains how the emission depends on the three-dimensional shape of the plasma.

Packaging at The ConFab

Wed, 9 Sep 2013
At The ConFab conference in Las Vegas in June, Mike Ma, VP of Corporate R&D at Siliconware (SPIL), announced a new business model for interposer based SiP’s, namely the “turnkey OSAT model.” In his presentation “The expanding Role of OSATS in the Era of System Integration,” Ma looked at the obstacles to 2.5/3D implementation and came up with the conclusion that cost is still a significant deterrent to all segments.

Package level integration: challenges and opportunities

Wed, 9 Sep 2013
A wide array of package level integration technologies now available to chip and system designers are reviewed.

STMicroelectronics reveals new micro-packaged device product family

Tue, 9 Sep 2013
Next-generation integrated devices for matching, filtering and protection help shrink circuit size and boost end-product performance.

Micron ships first samples of Hybrid Memory Cube

Wed, 9 Sep 2013
Micron Technology, Inc. announced today that it is shipping 2GB Hybrid Memory Cube (HMC) engineering samples.

3D and 2.5D Integration: A Status Report Live Event

Thu, 6 Jun 2012

This webcast will explore the present status of 2.5 and 3D integration, including TSV formation.

What chipmakers will need to address growing complexity, cost of IC design and yield ramps

Mon, 6 Jun 2015
As these early days of the Internet of Things show the network’s promise and reveal technological challenges that could threaten its ability to meet user expectations in the years ahead, technology providers will be charged with supplying the solutions that will meet those challenges.

Stanford and UT Austin professors to be honored at annual SRC TECHCON

Thu, 9 Sep 2013
Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, will honor professors from Stanford University and University of Texas at Austin with awards for chip-related research and education at SRC’s annual TECHCON conference Sept. 9-10.

GE acquires Imbera

Thu, 9 Sep 2013
GE Healthcare Finland Oy, in partnership with GE Idea Works, announced today that it has completed the acquisition of Imbera Electronics Oy.

3D-IC: Two for one

Wed, 9 Sep 2013
Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about upcoming events related to 3D ICs.

Nordic Semiconductor launches world’s first concurrent ANT+ and Bluetooth low energy combo chip

Wed, 10 Oct 2013
Ultra low power (ULP) RF specialist Nordic Semiconductor ASA today announces the release of the world's first multi-protocol SoC solution offering concurrent ANT+ and Bluetooth low energy wireless communication natively in a single chip.

Monolithic 3D chip fabricated without TSVs

Fri, 10 Oct 2013
Researchers from Taiwan’s National Nano Device Laboratories avoided the use of TSVs by fabricating a monolithic sub-50nm 3D using a novel CMP technique.

Samsung starts mass producing industry’s first 3D vertical NAND flash

Tue, 8 Aug 2013

New technology represents a breakthrough in overcoming NAND scaling limit and ushers in a new 3D memory era.

Monolithic 3D is now in production: Samsung starts mass producing first 3D vertical NAND flash

Tue, 8 Aug 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about Samsung's recent announcement on 3D vertical NAND.

Monolithic 3D is now on the roadmap for 2019

Thu, 8 Aug 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about the appearance of 3D integration on several roadmaps.

Samsung introduces world’s first 3D V-NAND-based SSD

Wed, 8 Aug 2013

Samsung today introduced the first solid state drive (SSD) based on its recently released 3D V-NAND technology. Samsung announced its new SSD, designed for use in enterprise servers and data centers, during a keynote at the Flash Memory Summit 2013.

Entegris and imec collaborate on 3D wafer handling and shipping challenges

Wed, 8 Aug 2013

Entegris, Inc. and imec announced they are collaborating to advance the development and broaden the adoption of 3D integrated circuits.

Dow Corning joins imec for advancement of enabling technologies for 3D-IC

Tue, 7 Jul 2013

Dow Corning announced Monday that it is among the newest member organizations to join imec, a leading research center for the advancement of nano-electronics.

Alchimer signs collaboration with CEA-Leti

Tue, 7 Jul 2013

Alchimer, S.A. today announced a collaboration with the French research institute CEA-Leti to evaluate and implement Alchimer's wet deposition processes for 300mm high-volume manufacturing.

SEMICON West R&D panel discusses the future of semiconductor technology

Wed, 7 Jul 2013

Leaders of research consortia from around the world sat down to share updates and insights with SEMICON West attendees on Wednesday morning.

Getting ready for 10/100/20 – Europe’s manufacturing initiative is underway

Tue, 7 Jul 2013

Europe’s recently launched industrial strategy to reinforce micro- and nanoelectronics manufacturing is more than just a vision — it’s a major opportunity for equipment and material suppliers to participate to large-scale investment projects, increase their holding in key technologies and reach out to new customers and markets.

Hybrid Memory Cube nears engineering sample milestone

Wed, 7 Jul 2013

Engineering samples of The Hybrid Memory Cube (HMC) are expected this summer, with high volume manufacturing coming next year. It will be one of the first high volume devices employing 3D integration and through silicon vias (TSVs), employing a bottom logic layer and 4-8 stacked DRAM layers.

Brewer Science: Simpler bonding/debonding process needed

Thu, 7 Jul 2013

A variety of techniques and materials have been developed to successfully achieve bonding/debonding for 3D integration, but Tony Flaim, chief technology officer of Brewer Science (Rolla, MO) says they are still too complicated.

Rudolph announces new metrology suite for advanced packaging

Wed, 7 Jul 2013

Rudolph Technologies, Inc., a provider of process characterization, photolithography equipment and software for the semiconductor, FPD, LED and solar industries, today released three new application-specific configurations of its industry-leading NSX 320 Automated Macro Defect Inspection System.

EUV vs TSV: Which one will become production ready first?

Wed, 7 Jul 2013

Israel Beinglass, CTO of MonolithIC 3D Inc., blogs about roadmap misses and the relationship between two seemingly unrelated technologies. 

Cascade Microtech and imec successfully probe 25µm-diameter micro-bumps

Thu, 8 Aug 2013

Cascade Microtech, Inc. and imec today announced breakthroughs in probing stacked integrated circuits (3D-SICs), fueling an important growth engine for the semiconductor market.

Moore's Law Dead By 2022: Crying Wolf?

Fri, 8 Aug 2013
Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about recent predictions regarding the demise of continued scaling.

Dow Corning and EV Group to collaborate on temporary bonding materials for 3D-IC

Tue, 9 Sep 2013
EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, announced today that Dow Corning has joined its network of top technology providers to support EVG's LowTemp platform for room-temperature wafer bonding and debonding processes.

EV Group unveils new via-filling process to improve reliability of 3D-IC/TSV packaging

Wed, 9 Sep 2013
EV Group, a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled a new polymer via-filling process for 3D-IC/through-silicon-via semiconductor packaging applications.

Collaboration needed on 3D-IC

Thu, 9 Sep 2013
The history of semiconductors has been a history of collaboration. Today, a similar industry-wide collaborative approach to 3D stacked ICs is needed to reach widespread 3D-IC adoption and continue the amazing progress our industry has historically achieved.

Blog Review October 14 2013

Mon, 10 Oct 2013
Recent blogs address semiconductors in healthcare (blood cell sorters), FinFETs and logic roadmaps, 450mm progress, panel level embedded tech, materials innovation, options to reduce mask write time, SOI and EUV.

IBM develops sub-20nm nanofluidic channels for lab-on-chip

Tue, 10 Oct 2013
At IEDM, IBM researchers will report on a CMOS-compatible 200 mm wafer-scale sub-20nm nanochannel fabrication method that enables stretching, translocation and real-time fluorescence microscopy imaging of single DNA molecules.

Rising demand for array IC packaging

Tue, 10 Oct 2013
Small form factor, high speed and performance, and high bandwidth capability with low battery consumption are desired traits for many packaging solutions for integrated circuits (ICs).

Laser thermal anneal to boost performance of 3D memory devices

Wed, 10 Oct 2013
Nanoelectronics research center imec and Excico have successfully demonstrated the application of laser thermal anneal (LTA) to boost the current in vertical polysilicon channel devices for 3D memory.

Scaling makes monolithic 3D IC practical

Mon, 10 Oct 2013
In the 1960s, James Early of Bell Labs proposed three-dimensional structures as a natural evolution for integrated circuits. Since then many attempts have been made to develop such a technology.

Memory materials revolution highlighted at SMC

Wed, 10 Oct 2013
While the number of materials used in semiconductor logic will increase approximately 50 percent in the transition from 32nm to 22nm production, the materials revolution in memory will be even more pronounced, challenging developers, manufacturers, equipment, and materials suppliers, according to experts speaking at the SEMI Strategic Materials Conference 2013, held in Santa Clara on October 16-17.

EU project to industrialize world record high-density capacitors

Wed, 10 Oct 2013
CEA-Leti, Fraunhofer IPMS-CNT and three European companies have launched a two-year project to industrialize 3D integrated capacitors with world-record density using atomic layer deposition.

Silicon interposers, CoWoS and microbumps

Wed, 10 Oct 2013
At the recent ECTC conference, various presentations addressed silicon interposers for 2.5D (Shinko), CoWoS reliability (TSMC) and microbumping (imec).

Three-dimensional atomic force microscopy

Wed, 10 Oct 2013
3D atomic force microscopes can measure critical dimensions, line edge roughness and sidewall roughness in a way that is highly accurate, non-destructive and cost-effective.

Are we using Moore's name in vain?

Tue, 11 Nov 2013
Clearly Moore's law is about cost, and Gordon Moore’s observation was that the optimum number of components (nowadays - transistors) to achieve minimum cost will double every year.

SUSS MicroTec installs excimer laser stepper at Fraunhofer IZM Berlin

Wed, 11 Nov 2013
SUSS MicroTec has successfully installed an ELP300 excimer laser stepper to support next generation advanced packaging and 3D IC laser debonding applications at the Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin.

GLOBALFOUNDRIES demonstrates model for next-generation chip packaging technologies

Thu, 11 Nov 2013
Foundry 2.0 partnership with Open-Silicon and Amkor Technology yields successful 2.5D test vehicle project.

Can Intel beat TSMC?

Mon, 11 Nov 2013
It would seem that if Intel could scale transistor cost as they have done in the last 40 years then they could win these super high volume consumer-oriented designs where cost is extremely important. And TSMC is clearly taking this seriously.

Semiconductor industry leaders to examine the future of 3D NAND at Dec 10 event

Mon, 12 Dec 2013
Manufacturing 3D NAND designs requires overcoming formidable technical challenges to create extremely complex high-aspect-ratio structures.

Sankalp Semiconductor appoints Dan Clein into its management team

Tue, 12 Dec 2013
Sankalp Semiconductor Private Limited, a leading Analog Mixed-Signal services and solutions company from India, announced today the appointment of Mr. Dan Clein into its management team. Dan will be based out of the North America region.

Micron Technology appoints Rajan Rajgopal as VP of Quality

Wed, 12 Dec 2013
Micron Technology, Inc. today announced that the company has named Rajan Rajgopal, vice president of Quality.

Worldwide semiconductor revenue grew 5.2 percent in 2013

Wed, 12 Dec 2013
Worldwide semiconductor revenue totaled $315.4 billion in 2013, a 5.2 percent increase from 2012 revenue of $299.9 billion, according to preliminary results by Gartner, Inc.

CEA-Leti signs agreement with Qualcomm to assess sequential 3D technology

Mon, 12 Dec 2013
CEA-Leti today announced an agreement with Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated, to assess the feasibility and the value of Leti’s sequential 3D technology.

Micron's high-density 45nm serial NOR Flash doubles programming speed for embedded applications

Tue, 12 Dec 2013
Micron Technology, Inc. today announced the availability of 45nm Serial NOR Flash memory samples in 512Mb, 1Gb, and 2Gb densities with a standard SPI interface.

AMD and Hynix announce joint development of HBM memory stacks

Mon, 12 Dec 2013
3DIC memory, and therefore all of 2.5/3D technology, took one step closer to full commercialization last week with the HBM joint development announcement from AMD and Hynix at the RTI 3D ASIP meeting in Burlingame CA.

Micron revenue surges after Elpida deal officially closes

Mon, 12 Dec 2013
Micron Technology surged 130 percent in revenue during the third quarter as it finally closed its acquisition of bankrupt Elpida Memory of Japan, a vigorous ascent that also propelled the total market for dynamic random access memory (DRAM) to its best performance yet in 11 quarters.

Substrate impact on 2.5/3D IC costs

Thu, 1 Jan 2014
At the recent Georgia Tech Global Interposer Technology (GIT) Workshop in Atlanta, the pervasive theme appeared to be whether a change in substrate is required to lower overall costs and help drive HVM (high volume manufacturing) applications.

Imec, AlixPartners to develop model for lowering costs of advanced semiconductor tech

Mon, 1 Jan 2014
Patterning options for N10/N7 nodes, advanced packaging solutions and 3D NAND memory to be targeted.

A bilayer temporary bonding solution for 3D-IC TSV fabrication

Thu, 1 Jan 2014
New technology eliminates the need for specialized equipment for wafer pre- or post-treatment.

Imec celebrates 30 years

Tue, 1 Jan 2014
Nanotechnology research and development center imec, today announced the celebration of its 30th anniversary.

Xilinx and University of Florida honored with SEMI Award for advancements in interposers and CMOS fab process

Wed, 1 Jan 2014
SEMI today announced that two teams — from the University of Florida and Xilinx — are recipients of the 2013 SEMI Award for North America.

3DIC market to reach $7.52B by 2019

Thu, 1 Jan 2014
The market for 3DICs globally is forecast to reach USD 7.52 billion by 2019, according to a new market report published by transparency market research.

Intel vs. TSMC: An Update

Tue, 1 Jan 2014
On January 14, 2014, we read on the Investors.com headlines page - Intel Seen Gaining Huge Pricing Advantage Over TSMC. Just three days later comes the responding headline: TSMC: We're "Far Superior" to Intel and Samsung as a Partner Fab.

Besi and Imec collaborate on thermocompression technology

Tue, 1 Jan 2014
Today, at the SEMI European 3D TSV Summit, nanoelectronics research center imec and Besi, a global equipment supplier for the semiconductor and electronics industries, announced they are joining forces to develop a thermocompression bonding solution for narrow-pitch die-to-die and die-to-wafer bonding with high accuracy and high throughput.

Natural 3D counterpart to graphene discovered

Tue, 1 Jan 2014
The discovery of what is essentially a 3D version of graphene promises exciting new things to come for the high-tech industry, including much faster transistors and far more compact hard drives.

Challenges and innovations on front-end and 3D TSV

Thu, 1 Jan 2013
Looking at 2014, we see challenges and innovations in both the front-end semiconductor and 3D TSV markets.

2014 Outlook: An era of unprecedented change

Fri, 1 Jan 2014
We asked leading industry experts and analysts to give us their perspectives on what we can expect in 2014.

Paradigm shift: Semi equipment tells the future

Mon, 1 Jan 2014
Looking at the semi-equipment booking should be the first step in any attempt to assess future semiconductor trends.

The 2014 European 2.5/3DIC Summit

Thu, 2 Feb 2014
SEMI’s second annual European 3D TSV Summit was held in Grenoble in late January. Three hundred and twenty attendees met to discuss the status of 2.5/3DIC and other advanced packaging technologies.

EV Group unveils high-volume manufacturing photoresist processing system

Tue, 2 Feb 2014
EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled its most advanced 300-mm photoresist processing system for logic and memory high-volume manufacturing.

SMIC and JCET establish joint venture for 12 inch bumping and testing

Fri, 2 Feb 2014
Semiconductor Manufacturing International Corporation, China's largest and most advanced semiconductor foundry, and Jiangsu Changjiang Electronics Technology Co., Ltd., the largest packaging service provider in China, jointly announced today a joint venture for 12" bumping and related testing.

North American semiconductor equipment industry posts January 2014 book-to-bill ratio of 1.04

Fri, 2 Feb 2014
A book-to-bill of 1.04 means that $104 worth of orders were received for every $100 of product billed for the month.

Laser spike annealing resolves sub-20nm logic device manufacturing challenges

Thu, 12 Dec 2014
LSA technology plays an enabling role to overcoming manufacturing challenges for sub-20nm logic devices.

Plug-and-play test strategy for 3D ICs

Tue, 3 Mar 2014
Three-dimensional (3D) ICs, chips assembled from multiple vertically stacked die, are coming. They offer better performance, reduced power, and improved yield.

Highlights from the IMAPS Device Packaging Conference

Mon, 3 Mar 2014
The annual IMAPS Device Packaging Conference in Ft McDowell AZ is always a source for the latest packaging information.

MEMSIC introduces the world's first monolithic and wafer level packaged 3D-axis accelerometer

Fri, 8 Aug 2014
MEMSIC, Inc., a MEMS sensing solution provider, announced today the availability of its MXC400xXC, the world's first monolithic 3D accelerometer, and also the first 3D accelerometer to utilize WLP technology.

In the permanent bonding market, EV Group is leading, Applied Materials and Tokyo Electron are merging

Fri, 4 Apr 2014
Permanent bonding technology is a key process for a wide range of applications in the semiconductor industry such as MEMS, advanced packaging, LED devices, and SOI substrate applications.

STS Semiconductor and Invensas to partner on high volume bond via array mobile solutions

Tue, 4 Apr 2014
Tessera Technologies, Inc. announced today that Invensas Corporation and South Korea-based STS Semiconductor & Telecommunications, a semiconductor assembly and test solution provider, have entered into an agreement to validate high volume manufacturing capability for Invensas' Bond Via Array (BVATM) technology for next generation smartphone and tablet customers.

Ziptronix licenses ZiBond to IO Semiconductor for RF applications

Wed, 4 Apr 2014
Ziptronix Inc., a provider of patented, low-temperature direct bonding technology for 3D integration, today announced a limited exclusive patent licensing agreement with IO Semiconductor (IOsemi) for application of its ZiBond technology for use in RF front-end devices for consumer mobile products.

SRC and UC Berkeley pursue more cost-effective approach to 3D chip integration

Wed, 5 May 2014
University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.

New materials and processes for advanced interconnects

Fri, 5 May 2014
Although on-chip interconnects have not been scaling at the same speed as other parts of the chip, new capabilities enabled by graphene and CNTs, among other materials, could soon change that.

3D EDA brings together proven 2D solutions

Fri, 3 Mar 2014
With anticipated economic limits to the continuation of Moore’s Law now on the horizon, it seems that moving into the 3rd dimension (3D) by stacking multiple layers of integrated circuits (IC) will be the ultimate expression of CMOS technology.

Near-Zero Keep-Out Zone for Through Silicon Via Technology

Mon, 5 May 2013

Slideshow: What to look for at IITC 2014

Tue, 5 May 2014
The 17th annual IITC will be held May 21 – 23, 2014 in conjunction with the 31st AMC at the Doubletree Hotel in San Jose, California.

SPTS Technologies announces the Omega Rapier XE System for 300mm wafer silicon etch processing

Thu, 5 May 2014
SPTS Technologies, a supplier of advanced wafer processing solutions for the global semiconductor industry and related markets, today announced the launch of its Rapier XE system for 300mm wafer silicon etching.

Ziptronix and EV Group demonstrate submicron accuracies for wafer-to-wafer hybrid bonding

Tue, 5 May 2014
­ Ziptronix Inc. and EV Group today announced they have successfully achieved submicron post-bond alignment accuracy on customer-provided 300mm DRAM wafers.

Applied Materials enables cost-effective vertical integration of 3D chips

Wed, 5 May 2014
Applied Materials, Inc. today introduced the Endura Ventura PVD system that helps customers reduce the cost of fabricating smaller, lower power, high-performance integrated 3D chips.

IEEE Packaging Awards handed out at 2014 ECTC

Thu, 6 Jun 2014
The 2014 Electronic Component Technology Conference (ECTC) took place last week in Orlando Florida.

SEMI's 3DIC standards activities

Sat, 5 May 2013
I have said many times that it will be impossible for a complicated technology like 3DIC to ever become commercial without standardization.

GS Nanotech pioneers 3D packaging technology in Russia

Thu, 6 Jun 2014
GS Nanotech, microelectronics products development and manufacture center, plans to launch mass assembly of 3D stacked TSV (through-silicon via) microcircuits in next few years.

Micron collaborates with Intel on on-package memory solution, leveraging 3D memory technology

Mon, 6 Jun 2014
Micron Technology, Inc., a provider of advanced semiconductor solutions, today announced an ongoing collaboration with Intel to deliver an on-package memory solution for Intel's next-generation Xeon Phi processor, codenamed Knights Landing.

SPTS and CEA-Leti/Nanoelec collaborate on 3D-TSV

Tue, 6 Jun 2014
SPTS Technologies, a manufacturer of etch, deposition and thermal processing equipment for the semiconductor industry, today announced that it has signed an agreement with CEA-Leti in Grenoble, France, to develop 3D-TSV technologies.

ConFab panelists discuss optimizing R&D in the changing semi landscape

Tue, 6 Jun 2014
Overheard @The ConFab: “I feel the best I’ve felt about semi since 2009.” –Mike Noonen, Silicon Catalyst

EVG clears key barriers to 3DIC/TSV HVM with fusion wafer bonding solution

Mon, 6 Jun 2014
EV Group today unveiled the GEMINI FB XT—its next-generation fusion wafer bonding platform, which combines several performance breakthroughs to move the semiconductor industry closer to the goal of high-volume manufacturing (HVM) of 3D-ICs with through-silicon vias (TSVs).

European 3D TSV Summit: “Smarter system integration” theme to focus on both business and technology

Tue, 9 Sep 2014
On January 19-21, 2015, SEMI will hold its 3rd edition of the European 3D TSV Summit in Grenoble, France.

A*STAR and industry partners form S$200M semiconductor R&D joint labs

Thu, 7 Jul 2014
Four joint laboratories, representing a commitment of S$200m between private and public sectors, were launched today between A*STAR's Institute of Microelectronics (IME), and its 10 industry partners.

Fusion bonding for next-generation 3D-ICs

Thu, 7 Jul 2014
Recent developments in wafer bonding technology have demonstrated the ability to achieve improved bond alignment accuracy.

3D memory for future nanoelectronic systems

Sun, 7 Jul 2013
Bit-growth slows while specialized stacking accelerates innovation in future memory solutions for communications, energy, and health-care.

Materials matter — Enabling the future of IC fabrication and packaging

Thu, 7 Jul 2014
The SEMI Strategic Materials Conference, held September 30–October 1 in Santa Clara, Calif., will examine the drivers for new materials and how they impact material suppliers and the value chain they serve.

Si2 announces new director of 3DIC programs

Thu, 8 Aug 2014
The Silicon Integration Initiative (Si2), a global semiconductor standards consortium, announced today that Herb Reiter is joining the team of professionals in the role of Director, 3D IC Programs.

New ClassOne electroplater a "sellout" at SEMICON West

Mon, 8 Aug 2014
When ClassOne Technology introduced its new Solstice electroplating systems at SEMICON West last month they didn’t expect to actually sell their first production unit off the show floor, but that’s what happened.

Intel releases new packaging, test technologies for 14nm foundries

Wed, 8 Aug 2014
Intel Corporation today announced two new technologies for Intel Custom Foundry customers that need cost-effective advanced packaging and test technologies.

SEMICON Taiwan 2014 opens today with spotlight on 3D-IC, sustainable manufacturing, and MEMS

Wed, 9 Sep 2014
Taiwanese chipmakers, LED manufacturers, and Outsourced Semiconductor Assembly and Test (OSAT) firms will spend firm nearly $24 billion in the next two years on equipment and materials, powering excitement for SEMICON Taiwan 2014, which opened today in Taipei.

Contour Semiconductor awarded three new U.S. patents

Thu, 9 Sep 2014
Contour Semiconductor, Inc., a developer of non-volatile memory technologies, today announced it has been awarded three new patents to back its Diode Transistor Memory (DTM) technology, the world's lowest production-cost, non-volatile memory technology.

Global shutter image sensors

Tue, 9 Sep 2014
Different GS pixel architectures and technologies are presented and performances compared.

Rudolph introduces new acoustic metrology and defect inspection technology

Thu, 9 Sep 2014
Rudolph Technologies has introduced its new SONUS Technology for measuring thick films and film stacks used in copper pillar bumps and for detecting defects, such as voids, in through silicon vias (TSVs).

TSMC delivers first fully functional 16 finFET networking processor

Mon, 9 Sep 2014
TSMC today announced that its has successfully produced the foundry segment's first fully functional ARM-based networking processor with FinFET technology, through its collaboration with HiSilicon Technologies Co, Ltd.

Tessera Technologies names Craig Mitchell as CTO and president of Invensas

Mon, 9 Sep 2014
Tessera Technologies, Inc. today announced it has named Craig Mitchell as chief technology officer for Tessera and president of Invensas Corporation, effective immediately.

A new dimension for integrated circuits: 3D nanomagnetic logic

Tue, 9 Sep 2014
Electrical engineers at the Technische Universität München (TUM) have demonstrated a new kind of building block for digital integrated circuits.

Samsung starts mass production of 8Gb DDR4 based on 20nm process technology

Wed, 10 Oct 2014
Samsung today announced that it is mass producing the industry’s most advanced 8-gigabit (Gb) DDR4 memory and 32-gigabyte (GB) module, both of which will be manufactured based on a new 20-nanometer (nm) process technology, for use in enterprise servers.

KLA-Tencor reveals 'leveraged recapitalization' plan and an expanded stock repurchase program

Fri, 10 Oct 2014
Yesterday, KLA-Tencor announced a plan to significantly accelerate its strategy to drive stockholder returns.

SEMI extends ASMC Call for Papers deadline to November 11

Thu, 10 Oct 2014
SEMI announced today that the deadline for presenters to submit an abstract for the 26th annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is extended to November 10.

Kandou introduces in-package chip interconnect enabling lower cost semiconductor solutions

Tue, 11 Nov 2014
Kandou Bus has announced the Glasswing family of chip interconnects targeted for in-package chip-to-chip links.

TSV integration is creating growth and significant interest in the equipment and materials industry

Tue, 11 Nov 2014
The materials market will grow from $789M in 2013 to over $2.1B with a CAGR of 18%.

European 3D TSV Summit 2015: Keynote speakers announced

Wed, 11 Nov 2014
This week, SEMI announced the keynote speakers for the third edition of the European 3D TSV Summit, event that will take place on January 19-21, 2015 in Grenoble, France.

Hybrid Memory Cube Consortium releases new specification

Mon, 11 Nov 2014
The Hybrid Memory Cube Consortium (HMCC), dedicated to the development and establishment of an industry-standard interface specification for Hybrid Memory Cube (HMC) technology, today announced the finalization and public availability of its HMCC 2.0 specification (HMCC 2.0).

1) “Pixel-Parallel” Image Processing

Tue, 11 Nov 2013

10) Nonvolatile Logic-in-Memory Technology

Tue, 11 Nov 2013

11) 3D Integration of Diverse Technologies for Self-Driving Vehicles

Tue, 11 Nov 2013

14) FinFETs Formed by Directed Self-Assembly

Tue, 11 Nov 2013

TSV based memory going to volume production: the era of 3DIC finally begins

Mon, 12 Dec 2014
With the recent Samsung announcement of mass production of 64 GB DDR4 DIMMs that use TSV technology for enterprise servers and cloud-based applications, all three of the major DRAM memory manufactures, Samsung, Hynix and Micron, have now announced the commercialization of TSV based memory architectures.

What to expect from the 3rd Edition of the European 3D TSV Summit

Thu, 12 Dec 2014
Interview with SEMI Europe’s Yann Guillou gives attendees a preview of the event.

3D TSV begins

Wed, 12 Dec 2014
“Engineering samples have already started to ship and preparation is on-going for entering volume manufacturing,” announces Yole.

Leti will discuss CoolCube technology for 3D transistor stacking at workshop preceding IEDM 2014

Thu, 12 Dec 2014
CEA-Leti will present its latest results on CoolCube, the technique for stacking transistors sequentially in the same process flow for 3D-VLSI, at a Dec. 14 workshop in San Francisco, Calif.

Synopsys and imec expand TCAD collaboration to 5nm and beyond

Tue, 12 Dec 2014
Synopsys, Inc. today announced the expansion of its collaboration with imec (nanoelectronics research center imec) to nanowire and other devices (FinFETs, Tunnel-FETs) targeting the 5-nanometer (nm) technology node and beyond.

Worth the detour: European 3D TSV Summit 2015 offers new outlooks on 2.5 and 3D technology

Tue, 12 Dec 2014
With just over a month left to go, industry experts are looking forward to the third edition of the European 3D TSV Summit (Jan 19-21, 2015 in Grenoble, France), this year focusing on “Enabling Smarter Systems.”

From transistors to bumps: Preparing SEM cross-sections by combining site-specific cleaving and broad ion milling

Thu, 12 Dec 2014
Cross section sample preparation is demonstrated using a workflow that combines High Accuracy Cleaving I(HAC) and Broad Ion Beam (BIB) milling.

The most expensive defect

Thu, 12 Dec 2014
Defects that aren’t detected inline cost fabs the most.

A little more patience required for 2.5/3D

Tue, 12 Dec 2014
There is an old proverb that states “All things Come to Those Who Wait.” I personally am not the waiting type wanting to get things done ASAP but most civilizations look at patience as a virtue.

European 3D TSV Summit 2015: What business for 3D smart systems?

Tue, 1 Jan 2015
SEMI Europe will ring in the New Year by holding the first major, international 3D TSV event of 2015. On January 19-21, members of the 3D TSV industry will convene in Grenoble, France for the 3rd edition of the European 3D TSV Summit.

ON Semiconductor demonstrates high efficiency 3D sensor stacking technology

Tue, 1 Jan 2015
ON Semiconductor has successfully characterized and demonstrated its first fully-functional stacked CMOS imaging sensor featuring a smaller die footprint, higher pixel performance and better power consumption compared to traditional monolithic non-stacked designs.

Orbotech announces collaboration between SPTS and Fraunhofer on process development of wafer level packaging

Thu, 1 Jan 2015
Orbotech Ltd. today announced that SPTS Technologies is collaborating with Fraunhofer IZM, an international institute specializing in applied and industrial contract research, on next generation wafer level packaging of microelectronic devices.

UC Berkeley Extension launches three online programs in semiconductor technology

Thu, 1 Jan 2015
UC Berkeley Extension announces three online integrated circuit (IC) semiconductor technology programs to meet the training needs of the surging worldwide semiconductor industry; the industry is predicted to reach $345 billion in sales this year.

Amkor Technology announces settlement with Tessera

Thu, 1 Jan 2015
Amkor Technology, Inc. today announced the settlement of its outstanding litigation and arbitration proceedings with Tessera, Inc.

2015 outlook: Tech trends and drivers

Tue, 1 Jan 2015
Leading industry experts provide their perspectives on what to expect in 2015. 3D devices and 3D integration, rising process complexity and “big data” are among the hot topics.

The CMOS image sensors industry is about to change, with major investment in manufacturing & design

Tue, 2 Feb 2015
Driven by mobile and automotive applications, the CIS industry is expected to grow at a CAGR of 10.6 percent from 2014 – 2020.

Spansion and XMC expand partnership to jointly develop 3D NAND

Mon, 2 Feb 2015
Spansion Inc. and XMC, China's fastest growing 300mm semiconductor foundry, today announced that the two companies will work together to develop and manufacture 3D NAND technology.

Mentor Graphics launches broadest embedded systems solution for industrial automation

Mon, 2 Feb 2015
Mentor Graphics Corporation today announced the embedded systems industry's broadest portfolio for industrial automation.

Amkor Technology names Susan Kim to Board of Directors

Wed, 2 Feb 2015
Amkor Technology, Inc. today announced that Susan Y. Kim has been appointed as a new member of the Company’s Board of Directors.

Samsung announces mass production of industry’s first 14nm finFET mobile application processor

Tue, 2 Feb 2015
Samsung Electronics Co., Ltd. announced that it has begun mass production of industry’s first mobile application processor using the advanced 14-nanometer (nm) FinFET process technology.

Micron appoints Robert Peglar as Vice President of Advanced Storage Solutions

Thu, 2 Feb 2015
Micron Technology, Inc. today announced that Robert Peglar has been named as vice president of Advanced Storage Solutions.

Thermal performance of 3DICs

Fri, 2 Feb 2015
3DICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies.

Applied Materials unveils breakthrough e-beam metrology tool for finFET transistors and 3D NAND devices

Mon, 2 Feb 2015
At the SPIE Advanced Lithography conference in San Jose, Calif., Applied Materials, Inc., today announced the industry's first in-line 3D CD SEM metrology tool for solving the challenges of measuring the high aspect ratio and complex features of 3D NAND and FinFET devices.

Imec demonstrates compact wavelength-division multiplexing CMOS silicon photonics transceiver

Thu, 2 Feb 2015
This week, at the 2015 International Solid State Circuits Conference (ISSCC), imec, in collaboration with Tyndall National Institute, the University of Leuven (KULeuven) and the Ghent University, demonstrated a 4x20Gb/s wavelength division multiplexing (WDM) hybrid CMOS silicon photonics transceive

Freescale and NXP agree to $40 Billion merger

Tue, 3 Mar 2015
Chipmaker NXP Semiconductors NV announced Sunday night that it has agreed to buy Freescale Semiconductor Ltd for $11.8 billion and merge business operations.

Embedded die in substrate: Challenges are still ahead

Tue, 3 Mar 2015
Embedded die in substrate: what are the next steps for the growth?

IRT Nanoelec and CMP team up to offer world’s first service for post-process 3D technologies on multi-project-wafer

Thu, 3 Mar 2015
IRT Nanoelec, an R&D consortium focused on ICT using micro- and nanoelectronics, and CMP, which provides prototyping and low-volume production of ICs and MEMS, are launching a platform for multi-project-wafer, post-process 3D integration (3D-MPW).

11 IC product categories to exceed total IC market growth in 2015

Thu, 3 Mar 2015
IC Insights’ March Update to the 2015 McClean Report (being released later this month) refreshes the forecasts for 33 major IC product categories through 2019.

XMC ships over 100 million units of backside illumination CMOS image sensors

Thu, 3 Mar 2015
XMC, a 300mm semiconductor manufacturing company, today announces it has shipped over 100 million Backside Illumination (BSI) CMOS Image Sensor (CIS) units.

Ziptronix licenses DBI hybrid bonding patents to Sony for advanced image sensor applications

Wed, 3 Mar 2015
Ziptronix Inc., a developer and provider of patented, low-temperature direct bonding technology for 3D integration, today announced a patent licensing agreement with Sony Corporation for application in advanced image sensors.

NXP-Freescale merger to result in world's eighth largest chip maker

Wed, 3 Mar 2015
The recent acquisition of Freescale Semiconductor by NXP Semiconductors would catapult the merged entity into the world’s eighth-largest chipmaker, positioning the newly minted giant for an even more formidable presence in key industrial sectors, according to IHS.

Optoelectronics, sensors/actuators, and discretes growth accelerates

Wed, 3 Mar 2015
After two years of sluggishness, O-S-D sales strengthen with an improving economy and a boost from new applications, says new 2015 report.

Micron and Intel unveil new 3D NAND flash memory

Thu, 3 Mar 2015
Micron Technology, Inc. and Intel Corporation today revealed the availability of their 3D NAND technology, the world’s highest-density flash memory.

Supplier Hub answers the needs of a changing semiconductor industry

Thu, 4 Apr 2015
Supplier Hub answers the needs of a changing semiconductor industry.

Imaging tomorrow’s components, acoustically

Thu, 4 Apr 2015
Packages are changing. Acoustic methods provide a way to image and analyze them.

Consider packaging requirements at the beginning, not the end, of the design cycle

Thu, 4 Apr 2015
Consider these eight issues where the packaging team should be closely involved with the circuit design team.

Duke University research advances testing of 3D integrated circuits for cost-effective development of electronics

Tue, 4 Apr 2015
Duke University researchers are working to advance the tools and methodologies used to test 3D integrated circuits (ICs), which promise to help ensure the ongoing development of higher performance, lower power semiconductor chips.

ClassOne enters ECD lab partnership with Shanghai Sinyang

Tue, 4 Apr 2015
Semiconductor equipment manufacturer ClassOne Technology announced today that it has signed a joint electrochemical deposition (ECD) applications lab agreement with Shanghai Sinyang Semiconductor Materials Co., Ltd.

A*STAR's IME and partners to enable low cost packaging technology for system scaling within smart devices

Wed, 4 Apr 2015
A*STAR’s Institute of Microelectronics (IME), together with industry partners, have formed a High-Density Fan-Out Wafer Level Packaging (FOWLP) consortium to extend FOWLP capabilities for applications in devices such as smart phones, tablets, navigation tools and gaming consoles.

KLA-Tencor introduces new portfolio for advanced semiconductor packaging

Thu, 4 Apr 2015
Today, KLA-Tencor Corporation announced two new systems that support advanced semiconductor packaging technologies: CIRCL-AP and ICOS T830.

Synopsys' modeling of 10nm parasitic variation effects ratified by open-source standards board

Tue, 4 Apr 2015
Synopsys, Inc. today announced new extensions to its open-source Interconnect Technology Format (ITF) which enable modeling of complex device and interconnect parasitic effects at the advanced 10-nanometer (nm) process node.

Surface matters: Huge reduction of heat conduction observed in flat silicon channels

Thu, 4 Apr 2015
A paper published in ACS Nano describes how the nanometre-scale topology and the chemical composition of the surface control the thermal conductivity of ultrathin silicon membranes.

Mentor Graphics releases design solutions for the independent engineer

Tue, 4 Apr 2015
Mentor Graphics Corporation this week announced the delivery of three new PADS family products starting at five thousand dollars to address the advancing needs of the independent engineer.

Co-design of chips, packages and boards

Wed, 5 May 2015
A new product from Mentor Graphics called Xpedition® Package Integrator provides a new methodology and platform in addition to a new suite of EDA tools.

ITRS 2.0: Heterogeneous integration

Wed, 5 May 2015
Interconnecting transistors and other components in the IC, in the package, on the printed circuit board and at the system and global network level, are where the future limitations in performance, power, latency and cost reside.

ASE and TDK announce plans for joint venture agreement

Fri, 5 May 2015
Driving towards market leadership in setting the industry standard for semiconductor miniaturization in portable and wearable consumer devices.

Moore's Law to keep on 28nm

Wed, 5 May 2015
Scaling is now bifurcating - some scaling on with 28/22nm, while other push below 14nm.

SRC names former Freescale CTO Ken Hansen as new president and CEO

Thu, 5 May 2015
Semiconductor Research Corporation (SRC) announced today that Ken Hansen has been appointed SRC’s new President and Chief Executive Officer (CEO), effective June 1.

imec and Lam Research develop novel metallization method

Tue, 5 May 2015
During the IEEE IITC conference in Grenoble, the nanoelectronics research center imec and Lam Research Corporation today presented a novel bottom-up prefill technique for vias and contacts.

UMC unveils UMC Auto Platform to enable automotive IC designs

Tue, 5 May 2015
United Microelectronics Corporation, a global semiconductor foundry, today unveiled its UMC Auto technology platform to target IC companies designing chips for automotive applications.

NXP and Stora Enso to develop intelligent packaging solutions

Fri, 5 May 2015
NXP Semiconductors and Stora Enso have entered into joint development of intelligent packaging solutions.

Diverse packaging and test issues up for debate at SEMICON West 2015

Fri, 5 May 2015
SEMI this week announced the SEMICON West 2015 test and packaging program agendas.

GLOBALFOUNDRIES solidifies 14nm finFET design infrastructure for next-generation chip design

Tue, 6 Jun 2015
GLOBALFOUNDRIES, a provider of advanced semiconductor manufacturing technology, today announced it has reached a critical milestone in providing a design infrastructure for its 14-nanometer (nm) FinFET process technology.

A novel characterization technique unveils the 3D structure of conductive filaments in resistive switching memories

Fri, 6 Jun 2015
Imec researchers have developed a novel technique – termed conductive atomic force microscopy tomography (or scalpel C-AFM) – that enables a three-dimensional characterization of emerging logic and memory devices.

Leti launches new Silicon Impulse FD-SOI Development Program

Mon, 6 Jun 2015
CEA-Leti announced today during the Design Automation Conference that seven partners have joined its new FD-SOI IC development program, Silicon Impulse.

Move over, 16nm – here comes 10nm chips

Mon, 6 Jun 2015
Taiwan Semiconductor Manufacturing wants you to know that they’re ready, willing, and able to help you design chips with 10-nanometer features.

ISSI agrees to merger terms with Cypress Semiconductor

Wed, 6 Jun 2015
Integrated Silicon Solution, Inc. today announced that it has finalized a definitive agreement to be acquired by Cypress Semiconductor Corporation for $20.25 per share in cash.

ASCENT project offers unparalleled access to European nanoelectronics infrastructure

Thu, 6 Jun 2015
Europe’s leading nanoelectronics institutes, Tyndall National Institute in Ireland, CEA-Leti in France and imec in Belgium, have entered a €4.7 million collaborative open-access project called ASCENT (Access to European Nanoelectronics Network).

More change for the chip industry

Thu, 6 Jun 2015
As if scaling to 7nm geometries and going vertical with FinFETs, TSVs and other emerging technologies wasn’t challenge enough, the emerging market for connected smart devices will bring more changes to the semiconductor sector. And then there’s 3D printing looming in the wings.

SK Hynix ramps production of high bandwidth memory

Tue, 6 Jun 2015
SK Hynix Inc. announced today that it is shipping mass production volumes of 1st generation High Bandwidth Memory (HBM1) based on SK hynix’s advanced 20nm-class DRAM process technology.

Leti workshop covers major trends in FD-SOI technologies

Tue, 6 Jun 2015
CEA-Leti will host a workshop on major trends in Fully Depleted Silicon-on-Insulator process and design technologies in connection with the 17th annual LetiDays Grenoble, June 24-25.

IRT Nanoelec partners achieve 3D chip-stacking technology & 3D network-on-chip framework

Thu, 7 Jul 2015
IRT Nanoelec, an R&D consortium focused on Information and Communication Technologies (ICT) using micro- and nanoelectronics, and its partners CEA-Leti, STMicroelectronics and Mentor Graphics have realized an innovative 3D chip called “3DNoC” to demonstrate the use of 3D stacking technology in scalable, complex digital systems-on-chip (SoCs).

Substrate innovation for extending Moore and more than Moore

Fri, 7 Jul 2015
Engineered SOI substrates are now a mainstream option for the semiconductor industry.

Applied Materials introduces high-performance ALD technology for the 3D era

Mon, 7 Jul 2015
Applied Materials, Inc. today unveiled the Applied Olympia ALD system, featuring a unique, modular architecture that delivers high-performance ALD technology to manufacturers of leading-edge 3D memory and logic chips.

GLOBALFOUNDRIES launches industry's first 22nm FD-SOI technology platform

Mon, 7 Jul 2015
GLOBALFOUNDRIES today launched a new semiconductor technology developed specifically to meet the ultra-low-power requirements of the next generation of connected devices.

Applied Materials' new etch system provides atomic-level precision

Mon, 7 Jul 2015
Applied Materials, Inc. today announced a next-generation etch tool, the Applied Centris Sym3 Etch system, featuring an entirely new chamber for atomic-level precision manufacturing.

Blood and tears at DAC

Tue, 7 Jul 2015
At this year’s Design Automation Conference (DAC) in San Francisco, Brian Otis, a Director at Google, talked about how hundreds of millions of people are at risk of diabetes – and how a smart contact lens that continuously monitors blood glucose levels and transmits the data to a smartphone might just be the ideal solution.

Small electronics companies spent $78.3B on semiconductors in 2014

Fri, 8 Aug 2015
Startups and small electronics companies spent $78.3 billion on semiconductors in 2014, representing 23 percent of the total market, compelling semiconductor companies to revisit their sales strategy to focus on the large number of smaller organizations than relying on big deals from large customers, research firm Gartner said.

“Above and beyond TSV for advanced ICs” - SEMI European 3D Summit 2016

Wed, 7 Jul 2015
SEMI today announced the fourth annual European 3D Summit. Entitled “European 3D Summit 2016: Above and Beyond TSV,” the advanced semiconductor Summit will take place on January 18-20, 2016 in Minatec in Grenoble, France.

Opportunities in packaging are driving photolithography equipment demand

Mon, 7 Jul 2015
Within the photolithography equipment market reaching $150M in 2014, advanced packaging applications experienced the strongest growth.

SEMICON West: The road forward is 3DIC

Fri, 7 Jul 2015
SEMICON West 2015 had a strong and rich undercurrent – the roadmap forward is most certainly 3DIC.

Samsung 3D TSV stacked DDR4 DRAM: the first analyzed memory product with via- middle TSV

Fri, 7 Jul 2015
According to Yole, 3D TSV technology is expected to reach $4.8B billion in revenues by 2019.

STATS ChipPAC appoints co-president and CEO

Wed, 8 Aug 2015
STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, announced today the promotion and appointment of Dr. Han Byung Joon as Co-President and Chief Executive Officer for the Company, together with Mr. Tan Lay Koon.

Toshiba develops world's first 16-die stacked NAND flash memory with TSV tech

Thu, 8 Aug 2015
Toshiba Corporation today announced the development of the world’s first 16-die (max.) stacked NAND flash memory utilizing Through Silicon Via (TSV) technology.

Toshiba launches 16MP CMOS image sensors targeting smartphones and tablets

Mon, 8 Aug 2015
Designed for use in smartphones and tablets, the backside-illuminated (BSI) chips are among the world's smallest class of CMOS image sensors, and achieve both high-performance image capture and low power consumption.

Rice U. discovery may boost memory technology

Tue, 8 Aug 2015
Scientists at Rice University have created a solid-state memory technology that allows for high-density storage with a minimum incidence of computer errors.

Comparison 1Y nanometer NAND architecture and beyond

Mon, 8 Aug 2015
Do we still think the 2D NAND Flash technologies have hit the scaling wall?

Leon Panetta to deliver keynote address at annual SIA Award Dinner

Tue, 8 Aug 2015
The Semiconductor Industry Association (SIA) announced former Defense Secretary Leon Panetta will deliver the keynote address at the upcoming SIA Award Dinner, taking place on Thursday, Dec. 3 in San Jose, Calif.

Update for exporters: Trade wins and delays

Tue, 8 Aug 2015
With trade policy dominating headlines in recent weeks, all eyes were on Maui in the waning days of August as trade ministers from twelve nations convened for perhaps the final time to finalize the Trans-Pacific Partnership (TPP).

Book-to-bill ratio reports indicate a solid year for the industry

Thu, 8 Aug 2015
A book-to-bill of 1.02 means that $102 worth of orders were received for every $100 of product billed for the month.

20th annual SEMICON Taiwan 2015 opens today

Wed, 9 Sep 2015
SEMICON Taiwan 2015 opened today starting a three-day event drawing over 43,000 attendees from electronics manufacturing.

Tessera to acquire Ziptronix for $39M

Fri, 8 Aug 2015
The acquisition expands on Tessera’s existing advanced packaging capabilities by adding a low-temperature wafer bonding technology platform that will accelerate delivery of 2.5D and 3D-IC solutions to semiconductor industry customers.

Advanced packaging and 3D-IC markets drive growth for EVG's automated 300mm polymer adhesive wafer bonding

Mon, 8 Aug 2015
EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that the company is experiencing strong demand for its automated 300mm polymer adhesive wafer bonding systems.

Automotive industry now the third largest end market for power semiconductors

Thu, 9 Sep 2015
In 2014, the automotive sector significantly outperformed the overall market average for semiconductors.

S3S - the conference for IoT technologies

Fri, 9 Sep 2015
The upcoming IEEE S3S Conference 2015 in Sonoma, CA, on October 5-8, will focus on key technologies for the IoT era.

UPDATED - Semiconductor Manufacturing: ASMC 2016 - Nov. 11 "call for papers" deadline

Tue, 11 Nov 2015
SEMI announced today that the deadline for presenters to submit an abstract for the 27th annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is November 2.

2016 Symposia on VLSI Technology and Circuits announces call for papers

Mon, 9 Sep 2015
The official Call for Papers has been issued for the 2016 Symposia on VLSI Technology and Circuits, to be held at the Hilton Hawaiian Village June 13-16, 2016 (Technology) and June 15-17, 2016 (Circuits).

2015 IEEE International Electron Devices meeting to showcase the latest technology developments in micro/nanoelectronics

Wed, 9 Sep 2015
At the 61st annual IEEE International Electron Devices Meeting (IEDM) subjects under discussion will encompass a range of topics critical to the continuing progress of the industry.

Novati Technologies launches advanced integrated sensor platform

Wed, 9 Sep 2015
Novati Technologies Inc. announced the availability of an advanced Integrated Sensor Platform, placing a wide variety of sensors onto multi-layer stacks of wafers in order to consume less power and perform significantly faster while reducing overall footprint.

Monolithic 3D - Game-Changing 2.0 at IEEE S3S

Mon, 10 Oct 2015
The path to alternative scaling is now open.

Entegris introduces SmartStack 300 mm contactless horizontal wafer shipper

Tue, 10 Oct 2015
Entegris, Inc. has expanded its wafer shipper family of products with the SmartStack (R) 300 mm Contactless Horizontal Wafer Shipper.

Lam Research to acquire KLA-Tencor

Wed, 10 Oct 2015
Lam Research Corporation (LRCX) and KLA-Tencor Corporation (KLAC) announced that they have entered into a definitive agreement for Lam Research to acquire all outstanding KLA-Tencor shares in a cash and stock transaction.

Successful industrialization of high-density 3D integrated silicon capacitors for ultra-miniaturized electronic components

Thu, 10 Oct 2015
Two years after the launch of the PICS project , three European SMEs, IPDiA, Picosun, and SENTECH Instruments along with CEA-Leti and Fraunhofer IPMS-CNT announce the major technological results achieved.

Ziptronix and Fraunhofer collaborate on low-cost 3D integration solutions

Fri, 10 Oct 2015
Ziptronix, Inc. announced it has entered into a development agreement with Fraunhofer IZM-ASSID.

Ultratech introduces superfast 4G+ low-cost in-line inspection system for patterned wafers

Wed, 11 Nov 2015
Ultratech, Inc. today introduced the Superfast 4G+ in-line, 3D topography inspection system.

Advances in thermo-compression bonding

Tue, 9 Sep 2015
At the 65th IEEE ECTC, several companies presented advances in thermos-compression bonding.

Photons on a chip set new paths for secure communications

Mon, 11 Nov 2015
Researchers from RMIT University in Melbourne have helped crack the code to ultra-secure telecommunications of the future in an international research project that could also expedite the advent of quantum computing.

Intel and ASM look to TCB

Tue, 11 Nov 2015
Is there any question that TCB is real and will be the next big bonding technology? The focus this month is more on this very important new assembly process from Intel and ASM.

Mobile sector continues to dominate the advanced packaging market; IoT looms on the horizon

Thu, 12 Dec 2015
Advanced packaging will reach 44% of packaging services and a revenue of US$ 30 billion by 2020.

Semiconductor sales: slight growth projected for next three years

Mon, 12 Dec 2015
Market projected to grow by 0.2 percent in 2015, 1.4 percent in 2016, and 3.1 percent in 2017.

Variation in build-up substrate layer thicknesses and its impact on FCBGA BLR performance

Tue, 12 Dec 2015
Subtleties in thicknesses between the alternating Cu metal and dielectric layers within a build-up substrate can impact BLR performance.

Advanced lithography and electroplating approach to form high-aspect ratio copper pillars

Tue, 12 Dec 2015
It is possible to fabricate copper pillars more than 100μm in height, with aspect ratios up to 6:1, using advanced packaging stepper lithography in conjunction with electroplating.

SEMI European 3D Summit: Beyond TSV in advanced ICs

Fri, 12 Dec 2015
SEMI this week announced details about the fourth annual European 3D Summit.

2016 bounce to modest gains

Mon, 12 Dec 2015
After deflated 2015, 3D leads the way.

Advanced semiconductor packaging drives materials consumption through 2019

Tue, 12 Dec 2015
The $18 billion semiconductor packaging materials will undergo steady single-digit unit volume growth for many material segments through 2019, including laminate substrates, IC leadframes, underfill, and copper wire.

SPTS Technologies installs a 300mm MEMS vapor HF etch release solution at CEA-Leti

Fri, 12 Dec 2015
SPTS Technologies has supplied CEA-Leti, one of Europe’s largest micro- and nanotechnologies research institutes, with its vapor HF etch release systems for 300mm microelectromechanical systems (MEMS) on CMOS development.

Koyanagi and Ramm win 3DIC Pioneering Award

Mon, 12 Dec 2015
At the 12th annual 3D ASIP [Architectures for Semiconductor Interconnect and Packaging] Conference, sponsored by RTI Int, in Redwood City CA last week, Professor Mitsumasa Koyanagi of Tohoku University and Dr. Peter Ramm of Fraunhofer EMFT were the conference's first recipients of the “3DIC Pioneer Award”.

Advanced packaging industry: What's new on the market?

Wed, 1 Jan 2016
The mobile sector is driving production and market growth; however a new market driver, IoT is on the horizon and is expected to have a significant impact on the advanced packaging industry.

SEMI Awards honor process and technology integration achievements

Thu, 1 Jan 2016
SEMI announced the recipients of the 2015 SEMI Awards for the Americas.

Smart Equipment Technology joins IRT Nanoelec 3D Integration Program

Fri, 1 Jan 2016
Will work with Leti, STMicroelectronics and Mentor Graphics to develop advanced 3D die-to-wafer stacking technologies using direct Cu-Cu bonding

Samsung, Apple continue to lead as top global semiconductor customers

Wed, 1 Jan 2016
Samsung Electronics and Apple remained the top semiconductor buyers in 2015, representing 17.7 percent of the market, according to Gartner, Inc.

Growing application of semiconductor ICs in the IoT driving global packaging and assembly equipment market

Thu, 1 Jan 2016
Technavio analysts forecast the global semiconductor packaging and assembly equipment market to post a CAGR of 4.7% by 2020, according to their latest report.

Yield and cost challenges at 16nm and beyond

Mon, 2 Feb 2016
A new 5D solution utilizes multiple types of metrology systems to identify and control fab-wide sources of pattern variation, with an intelligent analysis system to handle the data being generated.

SEMI launches new integrated packaging assembly and test group

Wed, 2 Feb 2016
SEMI announced today the launch of the European Semiconductor integrated Packaging and Test (ESiPAT) Special Interest Group.

FinFET technology market worth $35.12B by 2022

Thu, 2 Feb 2016
The FinFET technology market is expected to grow from $4.91 billion USD in 2015 to $35.12 billion by 2022, at a compound annual growth rate (CAGR) of 26.2% between 2016 and 2022.

EV Group joins IRT Nanoelec 3D Integration Program

Thu, 2 Feb 2016
EVG joins Leti, STMicroelectronics and Mentor Graphics to develop advanced 3D wafer-to-wafer bonding technologies.

UW scientists create ultrathin semiconductor heterostructures for new technologies

Fri, 2 Feb 2016
University of Washington scientists have successfully combined two different ultra thin semiconductors to make a new two-dimensional heterostructure with potential uses in clean energy and optically-active electronics.

New industry realities and opportunities at semiconductor manufacturing conference

Tue, 2 Feb 2016
The annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2016) will be held May 16-19 in Saratoga Springs, New York.

BiTS: The ever-shrinking package underscores emerging challenges and solutions

Thu, 2 Feb 2016
What’s the single area that is being most disrupted by emergent technologies like the Internet of Things (or the Internet of Vehicles) and Silicon Photonics? We think it’s packaging.

ARM and TSMC announce multi-year agreement to collaborate on 7nm FinFET process

Wed, 3 Mar 2016
ARM and TSMC announced a multi-year agreement to collaborate on a 7nm FinFET process technology which includes a design solution for future low-power, high-performance compute SoCs.

Amkor announces shipment of 700M RF and advanced SiP modules

Fri, 3 Mar 2016
Amkor Technology Inc. announced it has shipped 700 million RF and front-end advanced system-in-package (SiP) modules for mobile device applications.

How finFETs ended the service contract of silicide process

Fri, 3 Mar 2016
A look into how the silicide process has evolved over the years, trying to cope with the progress in scaling technology and why it could no longer be of service to finFET devices.

Texas Instruments names Devan Iyer Vice President

Tue, 3 Mar 2016
Texas Instruments Incorporated (TI) announced that Devan Iyer has been elected vice president of the company.

Rudolph adds high-speed 3D metrology to the NSX Series for advanced packaging process control

Thu, 4 Apr 2016
Rudolph Technologies, Inc. today announced the availability of new, high-speed 3D metrology on its flagship NSX Series, a highly-flexible inspection and measurement platform for process development and control of die-level interconnects.

Flip chip technology market worth $31.27B by 2022

Fri, 4 Apr 2016
The flip chip technology market is driven by factors such as increasing demand for miniaturization and high performance in electronic devices, and strong penetration in consumer electronics sector.

Leti extends collaboration with Qualcomm on CoolCube 3D integration technology

Tue, 4 Apr 2016
Leti, an institute of CEA Tech, today announced the continuation of its collaboration with Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated, to develop CoolCube.

The advanced packaging industry has reached its zenith

Thu, 4 Apr 2016
To overcome the current market and technology constraints taking place today within the semiconductor industry, new advanced packaging technologies have been developed by industrial companies.

Sandia National Laboratories licenses ZiBond and DBI technologies

Tue, 4 Apr 2016
Invensas Corporation, a wholly owned subsidiary of Tessera Technologies, Inc., announced today that Sandia National Laboratories signed a new license agreement for ZiBond and Direct Bond Interconnect (DBI) technologies.

Semiconductor experts chart chip industry's future direction beyond the "Moore's Law" horizon

Wed, 4 Apr 2016
Program unveiled for 2016 Symposia on VLSI Technology & Circuits – includes short courses, focus sessions, and panel discussions on "Inflections for a Smart Society" theme.

Invensas signs BVA technology license and development agreement with ASE

Thu, 5 May 2016
Tessera Technologies, Inc. announced today that its wholly owned subsidiary Invensas Corporation signed a new technology license and development agreement with Advanced Semiconductor Engineering, Inc.

STATS ChipPAC's fan-out wafer level packaging shipments exceed 1 billion units

Wed, 5 May 2016
Reflects strong demand for eWLB in mobile market with accelerating adoption in Internet of Things, wearables, MEMS and automotive applications.

EV Group receives multiple orders for GEMINI FB XT fusion bonder for 3D chip stacking production applications

Wed, 5 May 2016
EV Group (EVG) announced that it has received multiple orders for its GEMINI FB XT automated fusion wafer bonders from multiple leading device manufacturers.

Seven Top-20 semiconductor suppliers show double-digit declines

Thu, 5 May 2016
Qualcomm, Micron, and SK Hynix registered ≥25% drops, with total top-20 sales off by 6%.

Synopsys' Custom Compiler enabled for Samsung Foundry's 14nm finFET process

Fri, 5 May 2016
Synopsys, Inc. today announced that the company's Custom Compiler tool has been enabled by Samsung for 14 nanometer (nm) LPP and LPC FinFET production.

GLOBALFOUNDRIES releases performance-enhanced 130nm SiGe RF technology

Mon, 5 May 2016
GLOBALFOUNDRIES today announced a next-generation radio-frequency (RF) silicon solution for its Silicon Germanium (SiGe) high-performance technology portfolio.

Tessera files legal proceedings against Broadcom for patent infringement

Tue, 5 May 2016
Tessera Technologies, Inc. announced today that it and certain of its subsidiaries filed legal proceedings for patent infringement in both domestic and international jurisdictions against Broadcom.

Communications, computer systems drive IC sales across all regions

Wed, 5 May 2016
Automotive systems forecast to remain a major application in Europe and Japan.

An interview with Dr. Dongkai Shangguan

Wed, 6 Jun 2016
Dr. Dongkai Shangguan is currently the Chief Marketing Officer of STATS ChipPAC. Previously, Dongkai served as the founding CEO of the National Center for Advanced Packaging Co., Ltd. (“NCAP China”), worked for 10 years at Ford Motor Company in various technical and management functions, and for 11 years at Flextronics as Corporate Vice President of Global Advanced Technology.

Equipment spending up: 19 new fabs and lines to start construction

Fri, 6 Jun 2016
While semiconductor fab equipment spending is off to a slow start in 2016, it is expected to gain momentum through the end of the year. For 2016, 1.5 percent growth over 2015 is expected while 13 percent growth is forecast in 2017.

Global semiconductor sales decrease in April; Annual sales projected to dip slightly in 2016

Fri, 6 Jun 2016
The Semiconductor Industry Association (SIA) this week announced worldwide sales of semiconductors reached $25.8 billion for the month of April 2016.

Advanced Packaging Forum provides answers at SEMICON West 2016

Tue, 6 Jun 2016
Today, SEMI announced that the latest packaging solutions will be the topic of an in-depth session at the SEMICON West 2016 Advanced Packaging Forum - and on display on the exhibition floor.

Imec demonstrates junction-less gate-all-around lateral and vertical nanowire FET devices

Thu, 6 Jun 2016
The new GAA-NWFET is a promising candidate for advanced logic & analog/RF applications, and scaled SRAM cells.

Imec demonstrates gate-all-around MOSFETs with lateral silicon nanowires at scaled dimensions

Thu, 6 Jun 2016
Today, at the 2016 Symposia on VLSI Technology & Circuits, nano-electronics research center imec presented gate-all-around (GAA) n- and p-MOSFET devices made of vertically stacked horizontal silicon (Si) nanowires (NWs) with a diameter of only 8nm.

What is driving the advanced packaging market in China?

Thu, 6 Jun 2016
Driven by a strong semiconductor market outlook and aggressive investment in advanced packaging capability fueled by strong government support, advanced packaging revenue in China is expected to reach US$ 4.6 billion in 2020, against US$ 2.2 billion in 2015.

Building U.S. manufacturing ecosystems for emerging advanced packaging technologies

Wed, 6 Jun 2016
Emerging opportunities for advanced packaging solutions for heterogeneous integration include a lot more than logic, memory and sensors.

Power transistors to see less volatility in second half of this decade

Wed, 6 Jun 2016
Greater demand for energy efficiency in systems, cars, portable electronics, and new connections to the Internet of Things will steadily drive power transistor sales to new record-high levels in the next three years.

Ultratech receives multiple system, follow-on order for fan-out wafer-level packaging applications

Tue, 6 Jun 2016
Ultratech's AP300 lithography systems will be used for next-generation, high-volume, fan-out wafer-level packaging applications.

ALLVIA launches new product lines for Through Glass Vias and Through Quartz Vias

Wed, 6 Jun 2016
ALLVIA, Inc. has expanded its capacity into glass and quartz via manufacturing to accommodate customer requests in via-fill technology from silicon interposers to glass and quartz interposers.

A*STAR'S IME launches Chip-On-Wafer Consortium II and Cost Effective Interposer Consortium

Thu, 6 Jun 2016
A*STAR’s Institute of Microelectronics (IME) has partnered semiconductor companies to develop cost-effective solutions in 2.5D and 3D wafer-level integrated circuit (IC) packaging.

IC Insights lowers 2016 semiconductor market forecast to -1%

Fri, 7 Jul 2016
Weak global economy and poor DRAM market to drag down growth this year.

Kulicke & Soffa joins Chip-on-Wafer Consortium II

Fri, 7 Jul 2016
Kulicke & Soffa Industries, Inc. (NASDAQ: KLIC), a designer and manufacturer of semiconductor and LED assembly equipment, has joined A*STAR’s Institute of Microelectronics (IME)’s Chip-on-Wafer Consortium II, together with other major industry players.

Applied Materials' next-generation e-beam inspection system provides industry's highest resolution

Mon, 7 Jul 2016
Applied Materials, Inc. today announced its next-generation e-beam inspection system is delivering the highest resolution and image quality at the fastest throughput to leading foundry, logic, DRAM and 3D NAND customers as they move to advanced nodes.

Leti develops 3D network-on-chip to improve high-performance computing

Tue, 7 Jul 2016
Leti, a CEA Tech institute, today announced it has developed a new on-chip communications system to improve high-performance computing (HPC) that is faster and more energy efficient than current solutions and is compatible with 3D architectures.​

Shareholders of ChipMOS and ChipMOS Taiwan approve merger

Fri, 8 Aug 2016
ChipMOS TECHNOLOGIES (Bermuda) LTD. a provider of outsourced semiconductor assembly and test services, today announced that its shareholders have approved the merger of ChipMOS with and into ChipMOS TECHNOLOGIES INC.

Leti and Korea Institute of Science and Technology to collaborate on key growth areas for growing digital era

Wed, 7 Jul 2016
Leti, an institute of CEA Tech, and the Korea Institute of Science and Technology (KIST) today announced an agreement to jointly explore a variety of technologies, including monolithic 3D, neuromorphic architectures, non-volatile 3D memory, spintronics and ultra-low power semiconductors.

Toshiba and Western Digital celebrate opening of new Fab 2 semiconductor fabrication facility in Japan

Fri, 7 Jul 2016
Toshiba Corporation and Western Digital Corporation today celebrated the opening of the New Fab 2 semiconductor fabrication facility located in Yokkaichi, Mie Prefecture, Japan.

Amkor Technology receives "Device of the Year" for SWIFT semiconductor package

Wed, 7 Jul 2016
Amkor Technology, Inc. recently received the 3D InCites "Device of the Year" award during SEMICON West for its' SWIFT semiconductor package.

Solid State Technology Contributing Editor receives "Lifetime Achievement Award" for "Excellence in 3D Packaging Technologies"

Thu, 7 Jul 2016
Contributing editor and blogger Phil Garrou received the 3D InCites "Device of the Year" award during the 2016 SEMICON West conference for "Excellence in 3D Packaging Technologies."

2016 IEEE IEDM to showcase the latest tech developments in micro/nanoelectronics

Thu, 7 Jul 2016
Paper-submission deadline is August 10 this year; Supplier exhibition to be held in conjunction with technical program.

Applied Materials appoints Judy Bruner to Board of Directors

Mon, 7 Jul 2016
Applied Materials, Inc. today announced the appointment of Judy Bruner to serve on its Board of Directors. Ms. Bruner has also been appointed to serve as a member of the Audit Committee of the Board.

Evolving flip-chip technology boosting markets

Mon, 7 Jul 2016
New levels of performance of electronics technology have been enabled by flip-chip technology, fueling the growth of global markets for semiconductors, electronic devices, and a host of industrial and consumer products.

Chemical etching method helps transistors stand tall

Tue, 7 Jul 2016
University of Illinois researchers have developed a way to etch very tall, narrow finFETs, a type of transistor that forms a tall semiconductor "fin" for the current to travel over. The etching technique addresses many problems in trying to create 3-D devices, typically done now by stacking layers or carving out structures from a thicker semiconductor wafer.

China’s final chance to achieve its IC industry ambitions now underway

Wed, 7 Jul 2016
Over the past 20 years, China has become increasingly frustrated over the gap between its IC imports and indigenous IC production

Scientists find a way of acquiring graphene-like films from salts to boost nanoelectronics

Fri, 7 Jul 2016
Physicists use supercomputers to find a way of making 'imitation graphene' from salt.

POET Technologies announces milestone toward commercialization integrated opto-electronics tech platform

Wed, 8 Aug 2016
The milestone achieved is the first demonstration of functional Hetero-junction Field Effect Transistors (HFETs) down to 250nm effective gate lengths on the same proprietary epitaxy and utilizing the same integrated process sequence that was previously used to demonstrate high performance detectors.

Fan-Out Wafer Level Packaging: Breakthrough advantages and surmountable challenges

Tue, 8 Aug 2016
New wafer processing technologies overcome FOWLP’s technical hurdles, paving the way for a new generation of ultra compact, high I/O electronic devices.

Samsung showcases flash technologies to address growing requirements of storage systems

Fri, 8 Aug 2016
Samsung Electronics Co., Ltd. this week introduced a blueprint for next-generation flash memory solutions that will meet the ever-increasing demands of big data networks, cloud computing and real-time analysis.

Mentor Graphics launches new Xpedition Enterprise Platform

Mon, 8 Aug 2016
Mentor Graphics Corporation today announced the first phase of the new Xpedition printed circuit design (PCB) flow to address the increasing complexity of today's advanced systems designs.

Time to uncover the process mystery for IC designs

Mon, 8 Aug 2016
Semiconductor processes have long been a mystery for many circuit designers. They didn’t need to worry about how chips were fabricated most of the time, thanks to the many EDA innovations that make their jobs easier and complex designs possible.

Reno Sub-Systems secures first EVC matching network design win and large production order

Tue, 8 Aug 2016
Reno Sub-Systems today announced that it has secured its first platform design win for its Electronically Variable Capacitor (EVC) matching network.

Advanced packaging: Hot topic at SEMICON Taiwan 2016

Wed, 8 Aug 2016
SEMI announced today that over 43,000 visitors are expected to attend SEMICON Taiwan September 7-9 at the TWTC Nangang Exhibition Hall in Taipei.

New theory could lead to new generation of energy friendly optoelectronics

Mon, 8 Aug 2016
Researchers at Queen's University Belfast and ETH Zurich, Switzerland, have created a new theoretical framework which could help physicists and device engineers design better optoelectronics.

TowerJazz and SMIC’s sales forecast to surge in 2016

Tue, 8 Aug 2016
Total pure-play foundry market expected to jump 9% this year, up from 6% growth in 2015.

Will fan-out packaging be sustainable long-term?

Tue, 8 Aug 2016
2016 is a turning point for the Fan-Out market since both leaders, Apple and TSMC, changed the game and may create a trend of acceptance of Fan-Out packages

Littelfuse to acquire select product portfolio from ON Semiconductor

Fri, 8 Aug 2016
Littelfuse, Inc. today announced it has entered into definitive agreements to acquire the product portfolio of transient voltage suppression diodes, switching thyristors and insulated gate bipolar transistors for automotive ignition applications from ON Semiconductor Corporation for a combined purchase price of $104 million.

Plastic crystals could improve fabrication of memory devices

Wed, 8 Aug 2016
A novel 'plastic crystal' developed by Hokkaido University researchers has switching properties suitable for memory-related applications.

ASMC 2017 "Call for Papers" deadline is October 17

Thu, 9 Sep 2016
SEMI announced today that the deadline for presenters to submit an abstract for the annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is October 17.

Memory for future wearable electronics

Fri, 9 Sep 2016
Stretchable, flexible, reliable memory device inspired by the brain.

GLOBALFOUNDRIES unveils ecosystem partner program to accelerate innovation for tomorrow's connected systems

Thu, 9 Sep 2016
GLOBALFOUNDRIES today announced a new partner program, called FDXcelerator, an ecosystem designed to facilitate 22FDX system-on-chip (SoC) design and reduce time-to-market for its customers.

GLOBALFOUNDRIES extends FDX roadmap with 12nm FD-SOI technology

Thu, 9 Sep 2016
GLOBALFOUNDRIES today unveiled a new 12nm FD-SOI semiconductor technology, extending its leadership position by offering the industry's first multi-node FD-SOI roadmap.

GLOBALFOUNDRIES to deliver industry's leading-performance offering of 7nm FinFET technology

Thu, 9 Sep 2016
This technology provides more processing power for data centers, networking, premium mobile processors, and deep learning applications.

Nordson expands manufacturing center in northeast Ohio

Fri, 9 Sep 2016
Nordson Corporation today announced it plans to combine its existing screw and barrel operations in Youngstown, Ohio; New Castle, Pennsylvania; and Pulaski, Virginia into a single expanded manufacturing center of excellence in Austintown, Ohio.

Moore's Law did indeed stop at 28nm

Mon, 9 Sep 2016
As we have predicted two and a half years back, the industry is bifurcating, and just a few products pursue scaling to 7nm while the majority of designs stay on 28nm or older nodes.

≤200mm semiconductor manufacturing is here to stay

Tue, 9 Sep 2016
Ted Shafer of ASML reports on the highlights from the ≤200mm manufacturing session during SEMICON West, organized by the SEMI Secondary Equipment and Applications Special Interest Group.

Toshiba expands 24nm SLC NAND flash lineup to address industrial applications

Tue, 9 Sep 2016
Toshiba America Electronic Components, Inc. has expanded its family of 24nm single-level cell (SLC) NAND flash memory solutions.

Solid State Technology announces expanded conference for The ConFab 2017

Wed, 9 Sep 2016
The conference and networking event, will be held at the iconic Hotel del Coronado in San Diego on May 14-17, 2017.

SEMI European 3D Summit 2017: Creating high-density systems

Mon, 9 Sep 2016
The advanced semiconductor summit will take place on 23-25 January, 2017 at Minatec in Grenoble, France, with the theme "European 3D Summit 2017 – Creating High Density Systems."

TSMC recognizes Synopsys with three partner awards

Wed, 9 Sep 2016
Synopsys, Inc. today announced that TSMC is recognizing Synopsys with three "2016 Partner of the Year" awards for Interface IP and joint development of 7-nanometer (nm) mobile and HPC design platforms.

Mentor Graphics joins the WBGi Power Electronics Consortium in Japan

Mon, 10 Oct 2016
Mentor Graphics Corporation today announced that it has joined the Wide Band Gap integration (WBGi) power electronics consortium to participate in thermal management and power cycling initiatives.

Keynotes announced, registration open for SEMICON Japan 2016

Wed, 10 Oct 2016
Today, SEMI announced an exceptional lineup of keynotes at SEMICON Japan's "SuperTHEATER" focusing on innovation and insights into the future of the electronics supply chain.

Researchers use novel materials to build smallest transistor

Thu, 10 Oct 2016
In the quest for faster and more powerful computers and consumer electronics, big advances come in small packages.

3D TSV is for the development of heterogeneous interconnection, high end memory and performance applications

Thu, 10 Oct 2016
This year again, both market segments, high end and low end, are the main targets of the TSV technologies providers.

Murata to acquire IPDiA

Wed, 10 Oct 2016
Murata Manufacturing Co., Ltd. and IPDiA S.A. today announced that Murata Electronics Europe B.V., a wholly-owned subsidiary of Murata is about to acquire IPDiA, a 3D silicon capacitor technology developer headquartered in France, and IPDiA will become a subsidiary of Murata.

Samsung starts industry's first mass production of System-on-Chip with 10nm finFET technology

Mon, 10 Oct 2016
Samsung Electronics Co., Ltd. today announced that it has commenced mass production of System-on-Chip (SoC) products with 10-nanometer (nm) FinFET technology for which would make it first in the industry.

2016 IC market forecast raised from -2% to +1%

Wed, 10 Oct 2016
Rebound in DRAM market helps raise outlook for total IC market.

Ultralow power transistors could function for years without a battery

Fri, 10 Oct 2016
A new design for transistors which operate on 'scavenged' energy from their environment could form the basis for devices which function for months or years without a battery, and could be used for wearable or implantable electronics.

ams schedules 2017 multi-project wafer starts for analog foundry customers

Mon, 10 Oct 2016
180nm CMOS and HV-CMOS MPW runs are now manufactured in ams' 200mm fabrication facility in Austria.

Synopsys Custom Compiler certified for Samsung's 10nm process technology

Tue, 10 Oct 2016
Synopsys, Inc. today announced that its Custom Compiler tool has been certified by Samsung Electronics Co., Ltd. to support their 10-nanometer (nm) LPP (Low Power Plus) process.

Synopsys advances test and yield analysis solution for 7nm process node

Tue, 11 Nov 2016
Synopsys, Inc. today announced it expanded its test and yield analysis solution targeting FinFET-specific defects to enable higher quality testing, repair, diagnostics and yield analysis of advanced 7nm SoCs.

The Chinese advanced packaging ecosystem: Looking ahead

Wed, 11 Nov 2016
In 2015, more than US$1 billion was invested in China’s advanced packaging ecosystem, announces Yole in its report Status and Prospects for the Advanced Packaging Industry.

Next-gen low-noise imaging tech developed by Leti for French SME Pyxalis

Thu, 11 Nov 2016
Leti, an institute of CEA Tech, and PYXALIS, a French SME specializing in high-performance image sensors, today announced a new technology that lowers readout noise for image sensors down to 0.5 electron noise and dramatically improves low-light image sensing capabilities.

Lattice Semiconductor to be acquired by Canyon Bridge Capital Partners, Inc. for $1.3B

Thu, 11 Nov 2016
Lattice Semiconductor Corporation and Canyon Bridge Capital Partners, Inc. today announced that Lattice and Canyon Bridge Acquisition Company, Inc., an affiliate of Canyon Bridge, have signed a definitive agreement under which Canyon Bridge will acquire all outstanding shares of Lattice for approximately $1.3 billion.

The silicon photonics industry is ready for take-off

Tue, 11 Nov 2016
Silicon photonic technologies have reached the tipping point that precedes massive growth.

Qualcomm, Samsung collaborate on 10nm process tech for the latest Snapdragon 835 mobile processor

Thu, 11 Nov 2016
Qualcomm Incorporated today announced that its subsidiary, Qualcomm Technologies, Inc., and Samsung Electronics Co., Ltd., have extended their decade-long strategic foundry collaboration to manufacture Qualcomm Technologies' latest Snapdragon premium processor, Qualcomm Snapdragon 835, with Samsung's 10nm FinFET process technology.

ChipMOS and Tsinghua Unigroup agree to form joint-venture

Wed, 11 Nov 2016
ChipMOS TECHNOLOGIES INC. and Tsinghua Unigroup Ltd. today announced an agreement to form a joint-venture and to mutually terminate Tsinghua Unigroup's earlier private placement plan.

QuickLogic joins GLOBALFOUNDRIES FDXcelerator Partner Program

Thu, 12 Dec 2016
QuickLogic Corporation, a developer of ultra-low power programmable sensor processing, display bridge and programmable logic solutions, today announced that it has joined GLOBALFOUNDRIES' FDXcelerator Partner Program.

Tessera completes acquisition of DTS

Fri, 12 Dec 2016
Tessera Holding Corporation today announced it has completed the acquisition of DTS, Inc.

Five suppliers to hold 41% of global semiconductor marketshare in 2016

Wed, 12 Dec 2016
Two years of busy M&A activity boost marketshare among top suppliers.

ClassOne reports record sales, crediting WLP and "More than Moore"

Wed, 12 Dec 2016
“We’ve been seeing a steady increase in market interest and sales,” said ClassOne Technology President, Kevin Witt.

Global Semiconductor Alliance announces 2016 Award recipients

Fri, 12 Dec 2016
The Global Semiconductor Alliance (GSA) is proud to announce the award recipients honored at the 2016 GSA Awards Dinner Celebration that took place in Santa Clara, California.

Amkor completes product qualification of SWIFT packaging

Wed, 12 Dec 2016
Amkor Technology, Inc. today announced completion of product qualification for its innovative new Silicon Wafer Integrated Fan-Out Technology (SWIFT).

Embedded die: From incubation to high volume production

Thu, 12 Dec 2016
Embedded die in substrate platform has its own history and adoption scheme compared to other advanced packaging platforms.

North American semiconductor equipment industry posts November 2016 book-to-bill ratio of 0.96

Fri, 12 Dec 2016
A book-to-bill of 0.96 means that $96 worth of orders were received for every $100 of product billed for the month.

GLOBALFOUNDRIES expands Partner Program to speed time-to-market of FDX solutions

Fri, 12 Dec 2016
GLOBALFOUNDRIES today announced the addition of eight new partners to its growing FDXcelerator Program, including Advanced Semiconductor Engineering, Inc. (ASE Group), Amkor Technology, Infosys, Mentor Graphics, Rambus, Sasken, Sonics, and QuickLogic.

2017 Symposia on VLSI Technology & Circuits opens online submission for papers

Thu, 1 Jan 2017
Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits, to be held at the Rihga Royal Hotel in Kyoto, Japan from June 5 - 8, 2017.

Telecommunications light amplifier could strengthen integrity of transmitted data

Thu, 1 Jan 2017
Imagine a dim light which is insufficiently bright enough to illuminate a room. An amplifier for such a light would increase the brightness by increasing the number of photons emitted. Photonics researchers have created such a high gain optical amplifier that is compact enough to be placed on a chip. The developed amplifier would help to efficiently increase the power of the transmitted light before it is completely depleted through optical losses.

ON Semiconductor, Hexius Semiconductor expand scope of analog functionality for next gen mixed signal ASICs

Mon, 1 Jan 2017
ON Semiconductor announced a collaboration with Hexius Semiconductor to qualify several of their analog intellectual property (IP) blocks in its popular ONC18 0.18 µm CMOS process.

Memory market poised for strongest annual growth through 2021

Mon, 1 Jan 2017
Solid upside potential for DRAM, flash memory markets in 2017 and much of forecast period.

Pure-play foundry market surges 11% in 2016 to reach $50B

Thu, 1 Jan 2017
X-Fab, SMIC, and TowerJazz each grew by ≥30% last year.

$24B semiconductor assembly and testing services market poised for steady growth

Fri, 1 Jan 2017
This week, Future Market Insights (FMI) releases its latest report on the semiconductor assembly and testing services market.

Fire, rain, and M&A 

Thu, 1 Jan 2017
The expert panel, "The Future of M&A in the Semiconductor Industry," was a hot topic at SEMI's Industry Strategy Symposium (ISS) conference on January 11.

TechSearch International analysis predicts growth for fan-in and FO-WLP

Thu, 1 Jan 2017
TechSearch International predicts strong market growth for fan-in wafer level packages (WLPs) and fan- out WLP (FO-WLP).

Analog Devices announces changes to membership of Board of Directors

Thu, 1 Jan 2017
Richard Beyer and John Hodgson will retire from the Company's Board of Directors, effective as of the Company's 2017 Annual Meeting of Shareholders.

Imec and EVG demonstrate for the first time 1.8µm pitch overlay accuracy for wafer bonding

Fri, 1 Jan 2017
Breakthrough results pave the way to multi-layer 3D ICs with high density interconnects realized by automated wafer-to-wafer bonding technology.

STATS ChipPAC recognized for patent innovations for the seventh consecutive year by IEEE

Mon, 1 Jan 2017
STATS ChipPAC Pte. Ltd. announced today that it has been ranked among the world's top 10 semiconductor equipment manufacturing companies in the 2016 Patent Power Scorecards published by the Institute of Electrical and Electronics Engineers.

Executive viewpoints: 2017 outlook

Wed, 1 Jan 2017
Each year, Solid State Technology turns to industry leaders to hear viewpoints on the technological and economic outlook for the upcoming year. Read through these expert opinions on what to expect in 2017.

Global semiconductor chip packaging market dominated by 3DIC through-silicon via stacks packaging technique

Thu, 1 Jan 2017
The global semiconductor chip packaging market is expected to grow at a CAGR of more than 31% during the forecast period.

Top 3 trends impacting the global field-programmable gate array market through 2021

Fri, 1 Jan 2017
Technavio’s latest market research report on the global field-programmable gate array (FPGA) market provides an analysis of the most important trends expected to impact the market outlook from 2017-2021.

Axcelis announces multiple orders for 'Purion H' from  memory chipmakers in Asia Pacific

Mon, 1 Jan 2017
Axcelis Technologies, Inc. announced today that it has received orders for the Purion H high current implanter from two leading manufacturers of memory devices in the Asia Pacific region.

Samsung and Apple continued to lead as top global semiconductor customers in 2016

Wed, 2 Feb 2017
Samsung Electronics and Apple remained the top two semiconductor chip buyers in 2016, representing 18.2 percent of the total worldwide market, according to Gartner, Inc.

New photorelay from Toshiba features industry's smallest package

Mon, 2 Feb 2017
Toshiba America Electronic Components, Inc. (TAEC) has added a new photorelay to its extensive lineup of photocouplers.

Nexperia emerges as dynamic new force in discretes, logic and MOSFETs

Tue, 2 Feb 2017
Former Standard Products Division of NXP combines experience, product and operational excellence with customer focus and ambition.

IC market growth limited by narrow window of global GDP expansion

Thu, 2 Feb 2017
Significant and noticeable IC market growth closely tied to significant worldwide GDP growth.

Intel announces $7B investment in next-gen semiconductor fab in Arizona

Thu, 2 Feb 2017
The announcement was made by U.S. President Donald Trump and Intel CEO Brian Krzanich at the White House.

Grant Pierce named Chairman of the ESD Alliance Board of Directors

Thu, 2 Feb 2017
Grant A. Pierce, chief executive officer (CEO) of Sonics, Inc. was elected by the Board of Directors of the Electronic System Design Alliance (ESD Alliance) to serve as its chairman.

GlobalFoundries reveals expansion plans

Fri, 2 Feb 2017
The company is investing in its existing leading-edge fabs in the United States and Germany, expanding its footprint in China with a fab in Chengdu, and adding capacity for mainstream technologies in Singapore.

3D and 2.5D IC packaging market expected to be worth $170B by 2022

Tue, 2 Feb 2017
The market is expected to be worth USD 170.46 billion in 2022, at a CAGR of 38.30% between 2016 and 2022.

Huge growth in cloud memory changes semiconductor supply chain

Fri, 2 Feb 2017
The explosive growth in demand for internet bandwidth and cloud computing capacity brings a new set of technology challenges and opportunities for the semiconductor supply chain.

GE Ventures and Samsung Electro-Mechanics announce global microelectronics packaging patent agreement

Fri, 2 Feb 2017
With this partnership, SEMCO will license GE microelectronics packaging patent portfolio, covering the fabrication of substrates embedded with electronic circuits.

Invensas announces Teledyne DALSA sign DBI technology transfer and license agreement

Fri, 2 Feb 2017
Wafer bonding and 3D interconnect technology to enable delivery of next-generation MEMS and image sensor solutions.

SEMI appoints Ajit Manocha as president and CEO

Tue, 2 Feb 2017
SEMI today announced the appointment of Ajit Manocha as its president and CEO.

Dream Chip Technologies presents first 22nm FD-SOI silicon of new automotive driver assistance SoC

Mon, 2 Feb 2017
Dream Chip Technologies announced today the presentation of the industry`s first 22nm FD-SOI silicon for a new ADAS System-on-Chip (SoC) for automotive computer vision applications at the Mobile World Congress in Barcelona.

Advanced substrates: A key enabler of future advanced packaging solutions

Fri, 3 Mar 2017
Yole analysts provide an overview of advanced substrate technologies, markets, and supply chain.

January semiconductor sales up 14% compared to last year

Mon, 3 Mar 2017
Year-to-year growth is market's largest since November 2010; month-to-month sales decrease slightly.

Imec presents InGaAs TFET with sub-60 mV/decade sub-threshold swing

Mon, 3 Mar 2017
Promising alternative for MOSFET in future ultralow power chips.

Eutelsat, ST announce low-cost, low-power System-on-Chip for interactive satellite terminals

Wed, 3 Mar 2017
ST and Eutelsat complete development of chip for Eutelsat's next-generation SmartLNB.

NXP launches single-chip SoC with integrated microcontroller

Thu, 3 Mar 2017
NXP Semiconductors today announced the world's smallest single-chip SoC solution -- the MC9S08SUx microcontroller (MCU) family -- with an integrated 18V-to-5V LDO and MOSFET pre-driver that delivers ultra-high-voltage solution for drones, robots, power tools, DC fan, healthcare and other low-end brushless DC electric motor control (BLDC) applications.

Cadence expands capabilities of integrated design and analysis flow for TSMC InFO packaging technology

Mon, 3 Mar 2017
Cadence Design Systems, Inc. today announced new optimization capabilities within its holistic, integrated design flow for TSMC's advanced wafer-level Integrated Fan-Out (InFO) packaging technology.

Walker discusses emergence of new business models in semiconductor industry

Tue, 3 Mar 2017
Jim Walker, who retired from Gartner and is now consulting as World Level Packaging Concepts, gave a plenary talk at the recent IMAPS Device Packaging Conference in Scottsdale on the state of the semiconductor industry which contained some interesting perspectives on emerging new business models.

Cadence achieves certification for TSMC's 7nm process technology

Tue, 3 Mar 2017
Cadence Design Systems, Inc. today announced several new capabilities resulting from its close collaboration with TSMC to further 7nm FinFET design innovation for mobile and high-performance computing (HPC) platforms.

STATS ChipPAC achieves 1.5B unit milestone in fan-out wafer level packaging shipments

Wed, 3 Mar 2017
STATS ChipPAC Pte. Ltd., a provider of advanced semiconductor packaging and test services, announced today that it has shipped 1.5 billion fan-out wafer level packages (FOWLP), also known in the industry as embedded Wafer Level Ball Grid Array (eWLB).

Synopsys and TSMC collaborate to develop interface, analog and foundation IP for 12nm finFET process

Thu, 3 Mar 2017
Synopsys, Inc. (Nasdaq: SNPS) today announced its collaboration with TSMC to develop DesignWare Interface, Analog and Foundation IP for TSMC's 12FFC process.

Synopsys' IC Compiler II certified for TSMC's 12nm process technology

Thu, 3 Mar 2017
Synopsys, Inc. today announced that TSMC has certified the complete suite of products in the Synopsys Galaxy Design Platform for the most current version of 12nm FinFET process technology.

Samsung and eSilicon taped-out 14nm network processor with Rambus 28G SerDes solution

Wed, 3 Mar 2017
Samsung Electronics Co., Ltd.today announced a successful network processor tape-out based on Samsung’s 14LPP (Low-Power Plus) process technology in close collaboration with eSilicon and Rambus.

European SEMI Award honors advanced packaging technologists

Thu, 3 Mar 2017
At the SEMI Industry Strategy Symposium in Munich, SEMI announced recipients of the European SEMI Award for 2016.

Intel elects two new members to Board of Directors

Thu, 3 Mar 2017
Intel Corporation today announced that Omar Ishrak and Greg Smith have been elected to Intel’s board of directors.

Transphorm announces first automotive-qualified GaN FETs

Mon, 3 Mar 2017
Transphorm Inc. announced that its second generation, JEDEC-qualified high voltage gallium nitride (GaN) technology is now the industry's first GaN solution to earn automotive qualification -- having passed the Automotive Electronics Council’s AEC-Q101 stress tests for automotive-grade discrete semiconductors.

​ATTOPSEMI Technology joins FDXcelerator Program

Mon, 3 Mar 2017
ATTOPSEMI Technology, Ltd. today announced that it has joined GLOBALFOUNDRIES' FDXcelerator Partner Program, to provide a scalable, non-volatile one-time programmable (OTP) memory IP to be compatible with GF's 22FDX technology.

Synopsys' IC Validator used for physical sign-off on more than 100 finFET production tapeouts

Wed, 3 Mar 2017
Synopsys, Inc. today announced that its IC Validator physical verification product has been successfully used for signoff on more than 100 tapeouts at advanced FinFET nodes.

IC Insights more than doubles its 2017 IC market growth forecast

Thu, 3 Mar 2017
Huge spike in DRAM and NAND flash ASPs prompts market forecast revision to 11% increase.

Semiconductor industry sets out research needed to advance emerging technologies

Thu, 3 Mar 2017
New SIA-SRC report calls for robust research investments throughout the semiconductor industry and value chain.

IEEE unveils next lifecycle phase of the IRDS to drive computing industry beyond Moore’s Law

Fri, 3 Mar 2017
Series of nine white papers mark milestone effort for strategic initiative that identifies challenges and solutions to help guide future roadmaps.

Advanced packaging industry: What we could expect in 2017

Tue, 4 Apr 2017
2016 was the year of strong consolidations in the semiconductor industry. Yole Developpement (Yole) highlights many mergers and acquisitions with several billions of dollars transactions.

A novel method for the fabrication of active-matrix 3-D pressure sensors

Wed, 4 Apr 2017
A recent study, affiliated with UNIST has created a three-dimensional, tactile sensor that could detect wide pressure ranges from human body weight to a finger touch. This new sensor with transparent features is capable of generating an electrical signal based on the sensed touch actions, also, consumes far less electricity than conventional pressure sensors.

Cadence unveils expanded Virtuoso Advanced-Node Platform for 7nm processes

Wed, 4 Apr 2017
Cadence Design Systems, Inc. today announced the release of the new Virtuoso Advanced-Node Platform supporting advanced 7nm designs.

2016: The MOSFETs market recovered

Thu, 4 Apr 2017
In 2016, the MOSFET market recovered, after a minor downturn in 2015.

DDR4 set to account for largest share of DRAM market by architecture

Fri, 4 Apr 2017
DDR4 and DDR3 forecast to represent 97% of sizzling 2017 DRAM market.

Global ESD packaging market driven by the miniaturization of semiconductors, says Technavio

Mon, 4 Apr 2017
According to the latest market study released by Technavio, the electrostatic discharge (ESD) packaging market is projected to grow to USD 5.42 billion by 2021, at a CAGR of more than 8% over the forecast period.

Samsung completes qualification of its 2nd gen 10nm process technology

Wed, 4 Apr 2017
Samsung expands 10nm capacity, to be ready for production by the fourth quarter of this year.

Architecture innovation in the DRAM industry: How it affects firms’ sustainable competence

Mon, 3 Mar 2017
The technology leader in the DRAM industry has a greater advantage in terms of market share and profit.

SiPs simplify wireless IoT design

Mon, 3 Mar 2017
It takes a range of skills to create a successful business in the Internet of Things space, where chips sell for a few dollars and competition is intense. Circuit design and software support for multiple wireless standards must combine with manufacturing capabilities.

3D processing at Tohoku U

Mon, 2 Feb 2017
At the recent IEEE 3DIC Conference, Koyanagi and co-workers at Tohoku Univ reported on their studies of Ti as a 3D TSV barrier layer.

Air-gaps for finFETs shown at IEDM 2016

Wed, 12 Dec 2016
Researchers from IBM and GlobalFoundries will report on the first use of "air-gaps" as part of the dielectric insulation around active gates of "10nm-node" finFETs at the upcoming International Electron Devices Meeting (IEDM) of the IEEE.

Has SOI's turn come around again?

Wed, 12 Dec 2016
Analysts see another chance for Silicon-on-Insulator technology, as proponents claim technical and cost advantages for fully-depleted SOI.

CMOS image sensor update

Sun, 10 Oct 2016
Toshiba was the first to commercially implement CMOS image sensors with backside TSV last technologies in 2007. Many of us stated in 2007 that further advances could be obtained by removing the CMOS circuitry to a separate layer and forming a true 3D chip stack, but the technology imple- mentation had to wait while the industry first converted to back side imaging technology.

3D-NAND deposition and etch integration

Sun, 10 Oct 2016
Lam talks about process control and default roadmaps.

Preview: 2016 IEEE International Electron Devices Meeting

Sun, 10 Oct 2016
The 62nd annual IEDM will be held in San Francisco December 3 - 7, 2016.

TSMC's UBM-free fan-in WLCSP

Wed, 9 Sep 2016
At the 2016 ECTC Conference, TSMC discussed their UFI (UBM-Free Integration) Fan-In WLCSP technology which they claim enables large die fine pitch packages.

Deep dive into the Intel/ Micron 3D 32L FG-NAND

Wed, 9 Sep 2016
Key features of the cell structure, design and integration of the Micron 3D 32L FG-NAND device are discussed, and compared with Samsung’s 32L and 48L V-NAND device.

Will packaging make the difference for TSMC?

Tue, 6 Jun 2016
Earlier this year, a Taipei Times headline read “New packaging may spur TSMC growth” adding that despite its weak revenue growth guidance for this quarter, TSMC, might see stronger growth from next quarter thanks to its InFO (integrated fan out) packaging technology.

CoolCube 3D transistor stacking improves

Tue, 6 Jun 2016
Collaborating to build out design to fabrication ecosystem.

The Symposium on VLSI Technology: Technical highlights

Tue, 6 Jun 2016
Papers that address the theme "Inflections for a Smart Society" are highlighted.

Reducing down to 1/3 of thermal resistance by WOW technology for 3D DRAM application

Mon, 4 Apr 2017
Researchers at Tokyo institute of Technology presented a design guide for reducing 30% of thermal resistance for 3-dimensional (3D) stacked devices compared with the conventional ICs using solder bump joint structure.

Synopsys IC Validator physical signoff verifies 10 billion+ transistors within hours

Thu, 5 May 2017
Synopsys, Inc. today announced that its IC Validator was successfully deployed on some of the industry's largest and most advanced designs to accelerate design rule checking (DRC) closure.

2017 automotive IC market on pace for record year

Wed, 5 May 2017
22% forecast increase driven by system growth, rising ASPs for memory and logic devices.

Imec and Cascade Microtech develop first automatic probe system for advanced 3D chips

Wed, 5 May 2017
Imec and Cascade announced the successful development of a fully-automatic system for pre-bond testing of advanced 3D chips.

Volatility in electronic equipment supply chain

Thu, 6 Jun 2017
SEMI’s year-to-date worldwide semiconductor equipment billings year-to-date through March show a 59.6 percent gain to the same period last year.

"Billion Dollar Capex Club" forecast to swell to 15 companies in 2017

Thu, 6 Jun 2017
Top spenders expected to represent 83% of total semiconductor industry spending this year.

Seeing the invisible with a graphene-CMOS integrated device

Mon, 6 Jun 2017
Flagship researchers integrate graphene and quantum dots with CMOS technology to create an array of photodetectors, producing a high resolution image sensor.

Engineer unveils new spin on future of transistors with novel design

Mon, 6 Jun 2017
All-carbon, spintronic proposal could lead to smaller, better performing structures in electronics.

Mentor OSAT Alliance program streamlines IC high-density advanced packaging design and manufacturing

Mon, 6 Jun 2017
Mentor, a Siemens business, today announced that it has launched the Mentor OSAT (outsourced assembly and test) Alliance program to help drive ecosystem capabilities in support of new high-density advanced packaging (HDAP) technologies like 2.5D IC, 3D IC and fan-out wafer-level packaging (FOWLP) for customer integrated circuit (IC) designs.

SIA welcomes DARPA initiative to advance transformative semiconductor technologies

Tue, 6 Jun 2017
New program aims to progress beyond traditional scaling, catalyze next-generation semiconductor technologies.

Imec demonstrates breakthrough in CMOS-compatible ferroelectric memory

Wed, 6 Jun 2017
Imec has proved the validity of ferroelectric memory as a promising technology at various points in the memory hierarchy, and as a new technology for storage class memory -- today, it demonstrated the world's first a vertically stacked ferroelectric Al doped HfO2 device for NAND applications.

Artificial intelligence: A new era of the advanced packaging industry

Thu, 6 Jun 2017
AI is driving the development of 3D TSV and heterogeneous integration technologies.

GLOBALFOUNDRIES on track to deliver Leading-Performance 7nm FinFET technology

Wed, 6 Jun 2017
GLOBALFOUNDRIES this week announced the availability of its 7nm Leading-Performance (7LP) FinFET semiconductor technology, delivering a 40 percent generational performance boost.

Advanced packaging brings more value and cost reduction to future semiconductor products

Thu, 6 Jun 2017
Yole Developpement (Yole) confirms the consolidation of the advanced packaging industry, that is showing a steady growth between 2016 and 2022: +7% in revenue.

Cellphone IC sales will top total personal computing in 2017

Tue, 6 Jun 2017
Higher memory prices accelerate sales growth in both cellphones and personal computing systems but cellular handsets will become the largest application for ICs this year.

What TechInsights analysts are watching in 2017

Mon, 6 Jun 2017
TechInsights analysts share their view on where technology is going, how it’s changing, and what new developments are emerging.

Synopsys, GlobalFoundries collaborate to deliver design platform and IP enablement for 7nm finFET process

Tue, 6 Jun 2017
Synopsys, Inc. today announced the enablement of the Synopsys Design Platform and DesignWare Embedded Memory IP on GLOBALFOUNDRIES 7nm Leading-Performance (7LP) FinFET process technology.

It’s time for new innovation

Tue, 6 Jun 2017
What if the automotive industry had achieved the incredible pace of innovation as the semiconductor industry during the last 52 years?

HPC, chiplets and interposers

Thu, 6 Jun 2017
The need for ever more computational power continues to grow and exaflop (1018 ) capabilities may soon become necessary.

Leti and Fraunhofer team up to strengthen microelectronics innovation in France and Germany

Thu, 6 Jun 2017
Two European research institutes today announced their new collaboration to develop innovative, next-generation microelectronics technologies to spur innovation in their countries and strengthen European strategic and economic sovereignty.

How low can we go?

Tue, 7 Jul 2017
In the advanced CMOS technology programs ongoing in the Belgium city of Leuven, imec works to extend the building-blocks of integrated circuits (IC).

PLAT4M matures three silicon photonic platforms

Fri, 7 Jul 2017
Leti today announced that the European FP7 project PLAT4M has now been completed with results that exceeded expectations.

2H17 DRAM, NAND ASP growth to cool, but yearly growth strong

Tue, 7 Jul 2017
Record annual ASP growth rates forecast for both memory segments.

Hamburg researchers develop new transistor concept

Mon, 7 Jul 2017
Transistors, as used in billions on every computer chip, are nowadays based on semiconductor-type materials, usually silicon. As the demands for computer chips in laptops, tablets and smartphones continue to rise, new possibilities are being sought out to fabricate them inexpensively, energy-saving and flexibly.

Taiwan largest semiconductor materials market, as SEMICON Taiwan approaches

Wed, 7 Jul 2017
Taiwan is the world's largest consumer of semiconductor materials for the seventh consecutive year, bringing new opportunities in this increasingly critical sector.

2017 IEEE IEDM to showcase technology and device breakthroughs in logic, memory, bioelectronics, silicon photonics

Thu, 7 Jul 2017
Advances in semiconductor and related devices are driving significant progress in our increasingly digital world, and the place to learn about cutting-edge research in the field is the annual IEEE International Electron Devices Meeting (IEDM), to be held December 2-6, 2017 at the Hilton San Francisco Union Square hotel.

Gartner reports worldwide PC shipments declined 4.3% in second quarter of 2017

Fri, 7 Jul 2017
Worldwide PC shipments totaled 61.1 million units in the second quarter of 2017, a 4.3 percent decline from the second quarter of 2016, according to preliminary results by Gartner, Inc.

Laser debonding for ultrathin and stacked fan out packages

Thu, 7 Jul 2017
Fan-out packaging is an established technology for many mobile applications. Whereas early semiconductor packages have been single-chip packages, the continuing trend of expanding the wiring surface to support increased functionality has led to more complex packages, stacked packages, systems inpackageaswellashigh-performancepackages. With this development, fan-out technology is bridging a gap between cost-competitive packaging and high performance.

Overcoming challenges in 3D NAND volume manufacturing

Thu, 7 Jul 2017
As 3D NAND becomes the mainstream technology, its challenging roadmap poses opportunities for continued innovation.

Toshiba announces next generation client SSD with 64-layer 3D Flash memory

Tue, 8 Aug 2017
Toshiba America Electronic Components, Inc. (TAEC) announces the new SG6 series, the latest Toshiba client SSD to feature 64-layer, 3-bit-per-cell TLC (triple-level cell) BiCS FLASH to deliver better transfer speeds and power efficiency.

IntelliProp announces Gen-Z persistent memory controller combining DRAM and NAND

Tue, 8 Aug 2017
This controller combines DRAM and NAND and sits on the Gen-Z fabric, not the memory bus.

GLOBALFOUNDRIES demonstrates 2.5D high-bandwidth memory solution

Wed, 8 Aug 2017
GLOBALFOUNDRIES today announced that it has demonstrated silicon functionality of a 2.5D packaging solution for its high-performance 14nm FinFET FX-14 integrated design system for application-specific integrated circuits (ASICs).

Samsung introduces far-reaching V-NAND memory solutions to tackle data processing and storage challenges

Wed, 8 Aug 2017
Samsung Electronics Co., Ltd. has announced new V-NAND (Vertical NAND) memory solutions and technology that will address the pressing requirements of next-generation data processing and storage systems.

Vacuum subsystems: largest and fastest growing market segment

Mon, 8 Aug 2017
The increase in vacuum process intensity of the semiconductor industry means that by 2022, the market for vacuum subsystems could be up to 62 percent higher than today’s value of $1.9 billion.

DRAM, NAND flash, automotive analog/logic among bestgrowing ICs

Tue, 8 Aug 2017
Topping the chart of fastest-growing products is DRAM, which comes as no surprise given the strong rise of average selling prices in this segment throughout the first half of 2017.

Lam Research takes uniformity control to the edge

Wed, 8 Aug 2017
Chipmakers want every part of the wafer to yield good die. Advances in process technologies have just about made this a reality, even as feature dimensions continue to shrink and devices grow more complex.

PC DRAM contract price rose by over 10% sequentially and global DRAM revenue increase by 16.9% sequentially Q2

Fri, 8 Aug 2017
Global DRAM revenue reached a new historical high in the second quarter of 2017, according to DRAMeXchange.

Semiconductor industry capital spending forecast to jump 20% in 2017

Tue, 8 Aug 2017
Samsung remains the “wild card” with regard to 2H17 capital expenditures.

The ConFab announces mainstream semiconductor and emerging technologies 2018 conference focus

Mon, 8 Aug 2017
The ConFab – an exclusive conference and networking event for semiconductor manufacturing and design executives from leading device makers, OEMs, OSATs, fabs, suppliers and fabless/design companies – announces the 2018 event will be held at THE COSMOPOLITAN of LAS VEGAS on May 20-23.

DARPA's drive to keep the microelectronics revolution at full speed builds its own momentum

Fri, 9 Sep 2017
A dozen performer teams with DARPA’s CHIPS program convene to kick off an ambitious push for an era of versatile, plug-and-play "chiplets."

Update on the sale of Toshiba Memory Corporation

Fri, 9 Sep 2017
There have been media reports speculating that Toshiba will make a decision on Aug 31 at Toshiba’s Board of Directors meeting.

STMicroelectronics cooperating with MediaTek to integrate NFC tech into mobile-platform designs

Tue, 9 Sep 2017
STMicroelectronics (NYSE: STM) has announced the integration of its contactless NFC technology with MediaTek's mobile platforms.

Flex Logix joins TSMC IP Alliance Program

Tue, 9 Sep 2017
Flex Logix Technologies, Inc., the supplier of embedded FPGA IP and software, today announced that it has joined the TSMC IP Alliance Program included in TSMC's Open Innovation Platform.

Cadence delivers design and analysis flow enhancements for TSMC InFO and CoWoS 3D packaging tech

Wed, 9 Sep 2017
Cadence Design Systems, Inc. today announced new capabilities that complete its holistic, integrated design flow for TSMC's advanced wafer-level Integrated Fan-Out (InFO) packaging technology.

Soitec launches FD-SOI pilot line in Singapore

Wed, 9 Sep 2017
This is the first stage in beginning FD-SOI production in Singapore and providing multi-site FD-SOI substrate sourcing to the global semiconductor market.

Flex Logix wins TSMC Open Innovation Platform Partner Of The Year Award 2017

Fri, 9 Sep 2017
Flex Logix Technologies, Inc., a supplier of embedded FPGA IP and software, today announced it has won the TSMC Open Innovation Platform's Partner of the Year Award 2017 in the category of New IP for its EFLX embedded FPGA IP product.

DARPA calls for Monolithic 3D – 3DSoC

Tue, 9 Sep 2017
Learn all about Monolithic 3D at IEEE S3S.

Samsung completes qualification of 8nm LPP process

Wed, 10 Oct 2017
Samsung Electronics Co., Ltd. announced today that 8-nanometer (nm) FinFET process technology, 8LPP (Low Power Plus), has been qualified and is ready for production.

Leading-edge paves the way for pure-play foundry growth

Wed, 9 Sep 2017
Sales of ICs built using <40nm process technology forecast to rise 18% at pure-play foundries.

SEMICON Europa moves to Munich: Empowering innovation and shaping the value chain

Wed, 9 Sep 2017
New programs on Materials, Automotive, and Flexible Electronics expand SEMICON Europa's impact.

Samsung certifies Synopsys Design Platform for 28nm FD-SOI process technology

Mon, 9 Sep 2017
Synopsys, Inc. today announced that the Synopsys Design Platform has been fully certified for use on Samsung Foundry's 28FDS (FD-SOI) process technology.

Power transistor growth returns after volatile period

Wed, 9 Sep 2017
Inventory corrections, economic uncertainty, and price erosion derailed the power transistor market in the last five years, but the 2017 O-S-D Report sees steady modest growth ahead.

GLOBALFOUNDRIES delivers custom 14nm FinFET technology for IBM Systems

Fri, 9 Sep 2017
Jointly developed 14HP process is world’s only technology that leverages both FinFET and SOI.

Unprecedented opportunities in automotive electronics

Tue, 10 Oct 2017
Workshop will highlight rapid advancements in automotive electronics technologies and applications, and explore technical and business barriers and opportunities that are best addressed collectively across the supply chain.

New 3D packaging & integration committee

Mon, 10 Oct 2017
The SEMI International Standards Committee, at their SEMICON West 2017 meeting, approved the transformation of the existing 3D Stacked IC Committee and Assembly & Packaging Committee into a single, unified 3D Packaging and Integration Committee.

Comparing XPoint memory architecture with NAND and DRAM products

Tue, 10 Oct 2017
There has been a great deal of speculation around the composition of Intel’s Optane XPoint memory technology. TechInsights set about to find answers.

Monthly semiconductor sales reach $35B globally for first time in August

Wed, 10 Oct 2017
Worldwide sales up 24 percent year-to-year and 4 percent month-to-month; Americas market leads the way with growth of 39 percent year-to-year and 9 percent month-to month.

CMOS image sensor market to witness growth owing to high adoption of innovative technologies

Tue, 10 Oct 2017
The global CMOS image sensor market is expected to grow at a CAGR of more than 12% during the forecast period, according to Technavio’s latest market research.

Seeing the next dimension of computer chips

Wed, 10 Oct 2017
Researchers image perfectly smooth side-surfaces of 3-D silicon crystals with a scanning tunneling microscope, paving the way for smaller and faster computing devices.

Intel delivers 17-qubit superconducting chip with advanced packaging to QuTech

Thu, 10 Oct 2017
The new chip was fabricated by Intel and features a unique design to achieve improved yield and performance.

A 1,000x improvement in computer systems using current fabs and process

Thu, 10 Oct 2017
Next week, as part of the IEEE S3S 2017 program, MonolithIC 3D Inc. will present a paper (18.3) titled “A 1,000x Improvement in Computer Systems by Bridging the Processor Memory Gap”.

Leti to present update of CoolCube/3D VLSI tech developments at 2017 IEEE S3S

Fri, 10 Oct 2017
Leti, a research institute of CEA Tech, will hold a workshop on Oct. 17 to present updates on their progress developing CoolCube high-density 3D sequential, monolithic-integration technology, and their supporting design-and-manufacturing ecosystems.

China IC industry outlook

Tue, 10 Oct 2017
With an increasing presence in the global semiconductor manufacturing supply chain, the market opportunities in China are expanding dramatically.

2017 IEDM features rich technical program, focus sessions

Tue, 10 Oct 2017
Each year at the IEDM, the world's best technologists in micro/nano/bioelectronics converge to participate in a technical program consisting of more than 220 presentations, along with other events.

ASE, Amkor and JCET expected to top TrendForce's revenue ranking of OSAT providers for 2017

Wed, 10 Oct 2017
The annual revenue from the global IC testing and packaging industry for 2017 is estimated to grow by 2.2% to reach US$51.73 billion, according to the latest research from TrendForce.

Wafer-level packaging device shipments to overtake flip chip tech in 2018

Tue, 10 Oct 2017
The number of IC packages utilizing wafer-level packaging (WLP) will overtake flip chip shipments in 2018 and then continue growing at a compound annual growth rate of 15% (between 2014 and 2020) compared to just 5% for flip chip, according to the report recently published by The Information Network.

Deep-depletion: A new concept for MOSFETs

Thu, 10 Oct 2017
An international team of researchers has created a proof of concept that uses the deep-depletion regime in bulk-boron-doped diamond MOSFETs to increase hole channel carrier mobility.

How to solve the BEOL RC delay problem?

Tue, 11 Nov 2017
The RC delay issues started a few nodes ago, and the problems are becoming worse.

The intelligence that leads to artificial intelligence

Wed, 11 Nov 2017
Artificial intelligence (AI) may be a hot topic today, but SEMI has helped to incubate Big Data and AI since its founding.

DARPA's new initiative

Wed, 11 Nov 2017
Earlier this year, DARPA's Microsystems Technology Office (MTO) announced a new Electronics Resurgence Initiative (ERI) "to open pathways for far-reaching improvements in electronics performance well beyond the limits of traditional scaling."

Automotive electronic systems growth strongest through 2021

Thu, 11 Nov 2017
IC Market Drivers 2018 report ranks major end-use applications and their impact on IC market growth.

Semiconducting carbon nanotubes can reduce noise in carbon nanotube interconnects

Fri, 11 Nov 2017
Crosstalk and noise can become a major source of reliability problems of CNT based VLSI interconnects in the near future.

Soitec announces substrate breakthrough for 3D image sensing devices

Thu, 11 Nov 2017
Soitec, a designer and manufacturer of semiconductor materials for the electronics industry, today announced the latest generation of silicon-on-insulator (SOI) substrates in its Imager-SOI product line designed specifically for fabricating front-side imagers for near-infrared (NIR) applications including advanced 3D image sensors.

Google’s head of Quantum AI Lab to keynote at The ConFab 2018

Fri, 12 Dec 2017
The ConFab 2018, to be held at The Cosmopolitan of Las Vegas on May 21-23, is thrilled to announce the newest opening day Keynote speaker, Professor John M. Martinis.

Reveal previously invisible defects and contaminants in advanced packaging applications

Tue, 12 Dec 2017
A new illumination technology compares favorably to conventional bright field illumination.

Solutions for controlling resin bleed out

Tue, 12 Dec 2017
The hows and whys of resin bleed-out (RBO) are discussed, as well as the impact it makes and how to control it.

3D acoustic images expand their usefulness

Thu, 12 Dec 2017
3D acoustic imaging is useful for measuring the heights of bumps on BGAs, flip chips, and other devices. But it can also be used to image and quantify depth/height variation of features within a particular sample.

Leti memory breakthrough point way to significant improvements in SoC memories

Fri, 12 Dec 2017
Leti, a research institute of CEA Tech, demonstrated significant improvements in the field of memory systems at IEDM 2017 this week.

aveni extends copper interconnects to 5nm and below for BEOL integration

Tue, 12 Dec 2017
aveni S.A., developer and manufacturer of market-disrupting wet deposition technologies and chemistries for 2D interconnects and 3D through silicon via packaging, today announced it has obtained results that strongly support the continued use of copper in the back end of line (BEOL) for advanced interconnects, at and beyond the 5nm technology node.

IXYS announces 200V power MOSFETs with fast body diodes and lowest on-resistances

Thu, 12 Dec 2017
Fabricated using a charge compensation principle and IXYS' own process technology, these new MOSFETs exhibit the lowest on-state resistances in the industry.

Invensas completes DBI technology transfer to Teledyne DALSA

Fri, 12 Dec 2017
One of the world's largest independent MEMS foundries ready to manufacture MEMS and image sensor products utilizing Invensas wafer bonding and 3D interconnect technology.

EPC introduces 40V gallium nitride power transistor eight times smaller than equivalently rated MOSFETs

Tue, 12 Dec 2017
EPC2049 GaN power transistor offers power systems designers a 40 V, 5 mΩ power transistor about 8 times smaller than equivalently rated silicon MOSFETs for point of load converters, LiDAR, and low inductance motor drive.

SEMI European 3D Summit makes Dresden debut

Fri, 12 Dec 2017
The SEMI European 3D Summit will make its Dresden, Germany, debut 22-24 January, 2018, featuring a broader scope of 3D topics driving innovation and business opportunities in the 3D market.

Talent pipeline key to enabling industry growth: Takeaways from SEMI Member Forum

Wed, 1 Jan 2018
These were key highlights from a SEMI Member Forum in December that brought together industry representatives and students in Dresden to weigh in on job-skills challenges facing the electronics manufacturers and solutions for the industry to consider.

Worldwide PC shipments declined 2% in 4Q17 and 2.8% for the year

Fri, 1 Jan 2018
Amid market consolidation, the top four PC vendors accounted for 64% of shipments in 2017.

Everspin begins 40nm STT-MRAM volume production

Wed, 1 Jan 2018
Everspin Technologies, Inc., a developer and manufacturer of discrete and embedded MRAM, today announced the Company recorded revenue for its first 40nm 256Mb STT-MRAM products in the fourth quarter of 2017 and is in the process of ramping its volume production in 2018

Korea is at full throttle on memory investments

Wed, 1 Jan 2018
2017 proved to be record-setting year for the semiconductor industry. According to World Semiconductor Trade Statistics (WSTS), worldwide semiconductor market will have grown 20 percent, exceeding $400 billion for the first time.

Micron launches industry's first enterprise SATA solid state drives built on 64-layer 3D NAND technology

Tue, 1 Jan 2018
Micron Technology, Inc. today launched the Micron 5200 series of SATA solid state drives.

Gartner says Samsung and Apple extended their lead as top global semiconductor customers in 2017

Thu, 1 Jan 2018
Samsung Electronics and Apple remained the top two semiconductor chip buyers in 2017, representing 19.5 percent of the total worldwide market, according to Gartner, Inc.

GLOBALFOUNDRIES delivering 45nm RF SOI customer prototypes for 5G applications

Fri, 1 Jan 2018
Company's advanced 300mm RF SOI offering is ready for volume production.

Alpha and Omega Semiconductor announces the newest generation of XSPairFET

Tue, 1 Jan 2018
Alpha and Omega Semiconductor Limited (AOS) (Nasdaq:AOSL), a designer, developer and global supplier of a broad range of power semiconductors and power ICs, today introduced AONE36132, a 25V N-Channel MOSFET in a dual DFN 3.3x3.3 package which is ideal for synchronous buck converters.

Mobile system-on-chip designs, embedded processing lift MPU market

Thu, 2 Feb 2018
Though accounting for less than half of total MPU sales, data-handling cellphones, tablets, and MPUs for embedded processing applications to keep MPU market active through 2022.

Air Products to supply Samsung Electronics' second 3D V-NAND fab in western China

Fri, 2 Feb 2018
Air Products today announced it has been awarded the industrial gases supply for Samsung Electronics' second semiconductor fab in Xi'an, Shaanxi Province, western China.

Nordson MARCH MesoSPHERE Plasma Systems enable very high throughput processing for 3D and wafer-level package assembly

Fri, 2 Feb 2018
Nordson MARCH, a Nordson company introduces the MesoSPHERE Plasma System for very-high throughput processing of 3D and wafer-level packaging processes such as fan-in, fan-out, wafer-level, and panel-level – handling wafers up to 450mm and panels up to 480mm.

Annual semiconductor sales increase 21.6%, top $400B for first time

Mon, 2 Feb 2018
Global industry posts highest-ever annual, quarterly, and monthly sales.

SK Hynix ramps up enterprise SSDs with its 72-layer 512Gb 3D NAND flash

Mon, 2 Feb 2018
With its 72-Layer 512Gb (Gigabits) 3D NAND Flash chips, the company is paving the way for its full-fledged entrance to the high value-added eSSD market.

Samsung begins mass production of 256GB embedded Universal Flash Storage for automotive applications

Fri, 2 Feb 2018
Samsung Electronics Co., Ltd. today announced that it has begun mass production of a 256-gigabyte (GB) embedded Universal Flash Storage (eUFS) solution with advanced features based on automotive specifications from the JEDEC UFS 3.0 standard, for the first time in the industry.

MagnaChip offers 2nd-generation 0.13 micron BCD process technology with high-density embedded flash memory

Mon, 2 Feb 2018
MagnaChip Semiconductor Corporation announced today it now offers the 2nd generation of 0.13 micron BCD process technology integrated with high-density embedded Flash memory.

3D depth sensing & VCSEL technology surges: Key takeaways from SEMI Member Forum

Fri, 2 Feb 2018
Since Apple unveiled iPhone X with face-recognition functionality in early November 2017, interest in 3D sensing technology has reached fever pitch and attracted huge investments across the related supply chains.

Joseph Stockunas appointed to SEMI Foundation Board of Trustees

Wed, 2 Feb 2018
Nordson Corporation announces that the SEMI Foundation has appointed Joseph Stockunas, Corporate Vice President for Electronics Systems at Nordson Corporation and the immediate past chair of the SEMI North America Advisory Board, to the SEMI Foundation Board of Trustees in accordance with the association's by-laws.

Integrated circuit technology advances continue to amaze

Wed, 2 Feb 2018
Despite increasing costs of development, IC manufacturers are still making great strides.

Entering 2018 on solid ground

Thu, 2 Feb 2018
2017 finished on an upturn – both in the USA and globally. Based on consolidated fourth-quarter actual and estimated revenues of 213 large, global electronic manufactures, sales rose in excess of 7 percent in 4Q’17 vs. 4Q’16.

GLOBALFOUNDRIES strengthens 22FDX eMRAM platform with eVaderis' ultra-low power MCU reference design

Tue, 2 Feb 2018
Co-developed technology solution enables significant power and die size reductions for IoT and wearable products.

Work to do to keep the good times rolling

Fri, 3 Mar 2018
2017 was a terrific year for SEMI members. Chip revenues closed at nearly $440B, an impressive 22 percent year- over-year growth.

Executive viewpoints: 2018 outlook

Mon, 3 Mar 2018
Each year, Solid State Technology turns to industry leaders to hear viewpoints on the technological and economic outlook for the upcoming year. Read through these expert opinions on what to expect in 2018.

Are the major DRAM suppliers stunting DRAM demand?

Wed, 3 Mar 2018
Skyrocketing DRAM prices potentially open the door for startup Chinese competitors.

Synopsys collaborates with Samsung Foundry to develop DesignWare IP for Samsung 8nm finFET process

Thu, 3 Mar 2018
Synopsys, Inc. today announced a collaboration with Samsung Foundry to develop DesignWare Foundation IP for Samsung's 8nm Low Power Plus (8LPP) FinFET process technology.

Qualcomm Board names Jeffrey Henderson Non-Executive Chairman

Fri, 3 Mar 2018
The Board has discontinued the role of Executive Chairman, which was established in 2014 as part of a leadership transition plan, based on its belief that an independent Chairman is now more appropriate for Qualcomm. The Board has named Jeffrey W. Henderson, an independent Qualcomm director since 2016, to serve as Non-Executive Chairman.

IC Insights raises 2018 IC market forecast from 8% to 15%

Thu, 3 Mar 2018
Increased expectations for the DRAM and NAND flash markets spur upward revision.

The ConFab 2018 announces conference agenda and speakers

Fri, 3 Mar 2018
Browse this slideshow for a look at this year's speakers, keynotes, panel discussions, and special guests.

Everspin signs long-term patent license agreement with Alps Electric

Mon, 3 Mar 2018
Under the agreement, Alps and Everspin will mutually grant licenses to magnetoresistive-based 3D sensor patent portfolios for magnetoresistive sensor products.

SEMICON West 2018 to spotlight smart technologies, workforce development

Tue, 3 Mar 2018
SEMICON West has opened registration for the July 10-12, 2018, exposition at the Moscone Center in San Francisco, California.

U.S. trade tensions with China hit fever pitch

Wed, 3 Mar 2018
Stiff tariffs and the dismantling of longstanding trade agreements – cornerstones of these new actions – will ripple through the semiconductor industry with particularly damaging effect.

Automotive chip manufacturing in Japan drives innovation

Wed, 3 Mar 2018
In Tokyo, Shanghai, Moscow, London, Paris or New York – wherever you are in the world –Japanese vehicles passing by on the roadways are a common sight.

"Technology, Circuits & Systems for Smart Living" theme for 2018 Symposia on VLSI Technology & Circuits

Wed, 3 Mar 2018
Bringing together a technical program that encompasses 'big integration' of a number of critical industry trends -- machine learning, IoT, artificial intelligence, wearable/implantable biomedical applications, big data, and cloud computing -- the 2018 Symposia on VLSI Technology & Circuits will showcase a convergence of technologies needed for 'smart living.'

Synopsys acquires Silicon and Beyond Private Limited

Thu, 3 Mar 2018
Synopsys, Inc. today announced it has acquired Silicon and Beyond Private Limited, a provider of high-speed SerDes technology used in data intensive applications such as machine learning, cloud computing, and networking.

U.S. companies maintain largest share of fabless company IC sales

Fri, 3 Mar 2018
China-based companies show the largest fabless IC marketshare gain since 2010.

New insights from failures

Mon, 3 Mar 2018
To be able to guarantee the reliability of transistors, we have been conducting research for some years now at imec to see what happens when transistors operate properly and when they fail.

Optoelectronics, sensors/actuators, and discretes hit record-high sales

Thu, 3 Mar 2018
Total revenues in the three O-S-D market segments climbed 11% in 2017 -- the strongest growth rate since 2010 -- and continue to be driven by high demand for sensors, actuators, CMOS imaging devices, light sensors, laser transmitters, and power discretes.

China now world's largest consumer of semiconductor packaging equipment and materials

Mon, 4 Apr 2018
Fueled by heavy government investment, IC packaging and testing in China generated $29 billion in revenue in 2017, making China the world's largest consumer of packaging equipment and materials.

ON Semiconductor introduces digital image sensor with low light sensitivity and signal-noise ratio

Tue, 4 Apr 2018
ON Semiconductor introduced the industry’s first 1/1.7-inch 2.1 megapixel CMOS image sensor featuring ON Semiconductor’s newly developed 4.2μm Back Side Illuminated (BSI) pixels.

6 key takeaways from ISS Europe 2018

Wed, 4 Apr 2018
With its leading research and development hubs, materials and equipment companies and chipmakers, the EU is in a strategic position in the global electronics value chain to support the growth of emerging applications such as autonomous driving, internet of things, artificial intelligence and deep learning.

Toshiba releases automotive 40V N-channel power MOSFETs in new package

Wed, 4 Apr 2018
Reduced on-resistance from use of a small low-resistance package.

SEMI and TechSearch International report global semiconductor packaging materials market reaches $16.7B

Wed, 4 Apr 2018
SEMI, the industry association representing the global electronics manufacturing supply chain, and TechSearch International today reported that the global semiconductor packaging materials market reached $16.7 billion in 2017.

Nexperia secures $800M financing to fund future growth plans

Thu, 4 Apr 2018
Discrete semiconductor company’s refinancing supported by major global banks.

Semiconductor assembly and packaging services: Rising number of fabs is driving the market

Mon, 4 Apr 2018
Technavio market research analysts forecast the global semiconductor assembly and packaging services market to grow at a CAGR of close to 5% during the period 2018-2022, according to their latest report.

Orbotech's SPTS Technologies honored with Queen's Award for Enterprise in Innovation 2018

Tue, 4 Apr 2018
The award recognizes SPTS's development of novel physical vapor deposition (PVD) process solutions for Fan-Out Wafer Level Packaging (FOWLP) of semiconductor devices.

Arbe Robotics selects GlobalFoundries for its high-res imaging radar

Thu, 4 Apr 2018
Arbe Robotics' proprietary chipset leverages GF's 22FDX technology to deliver industry's first real-time 4D imaging radar for level 4 and 5 autonomous driving.

Samsung begins mass production of 10nm-class 16Gb LPDDR4X DRAM for automobiles

Thu, 4 Apr 2018
The latest LPDDR4X features high performance and energy efficiency while significantly raising the thermal endurance level for automotive applications that often need to operate in extreme environments.

TSMC certifies Synopsys Design platform for high-performance 7nm FinFET Plus technology

Mon, 4 Apr 2018
Synopsys, Inc. today announced certification of the Synopsys Design Platform with TSMC's latest Design Rule Manual (DRM) for advanced 7nm FinFET Plus process technology.

Cadence collaborates with TSMC to advance 5nm and 7nm+ mobile and HPC design innovation

Tue, 5 May 2018
Cadence Design Systems, Inc. today announced its continued collaboration with TSMC to further 5nm and 7nm+ FinFET design innovation for mobile and high-performance computing (HPC) platforms.

Mentor enhances tool portfolio for TSMC 5nm FinFET and 7nm FinFET Plus processes and wafer-on-wafer stacking technology

Tue, 5 May 2018
Mentor, a Siemens business, has announced that several tools in its Calibre nmPlatform and Analog FastSPICE (AFS) Platform have been certified by TSMC for the latest versions of TSMC's 5nm FinFET and 7nm FinFET Plus processes.

TowerJazz announces release of advanced 300mm 65nm BCD power management platform

Wed, 5 May 2018
TowerJazz today announced the release of its 300mm 65nm BCD (Bipolar-CMOS-DMOS) process, the most advanced power management platform for up to 16V operation and 24V maximum voltage.

ALLVIA adds capabilities for through-quartz vias

Wed, 5 May 2018
To meet growing market demand for high-density 2.5D and 3D stacked semiconductor solutions, Silicon Valley-based ALLVIA, Inc. has expanded its in-house capabilities to include the formation of through-quartz vias (TQV) ranging from 15 microns in diameter and 100 microns deep to 50 microns in diameter and 250 microns deep.

Global semiconductor packaging materials market tops $16B

Mon, 5 May 2018
The global semiconductor packaging materials market reached $16.7 billion in 2017. While slower growth of smartphones and personal computers -- the industry’s traditional drivers -- is reducing material consumption, the slowdown was offset by strong unit growth in the cryptocurrency market in 2017 and early 2018.

Semtech announces acquisition of IC Interconnect

Mon, 5 May 2018
Semtech Corporation, a supplier of high performance analog, mixed-signal semiconductors and advanced algorithms, today announced it has acquired substantially all the assets of IC Interconnect, Inc.

CMOS image sensor sales stay on record-breaking pace

Tue, 5 May 2018
Embedded imaging applications in cars, security, machine vision, medical, virtual reality, and other new uses will offset slow growth in camera phones, says new report.

TowerJazz and Newsight Imaging announce advanced CMOS image sensor chips for LiDAR

Wed, 5 May 2018
TowerJazz, the global specialty foundry leader, and Newsight Imaging, today announced production of Newsight's advanced CMOS image sensor (CIS) chips and camera modules, customized for very high volume LiDAR and machine vision markets, combining sensors, digital algorithms and pixel array on the same chip.

Presto Engineering joins GLOBALFOUNDRIES Ecosystem as ASIC Partner

Tue, 5 May 2018
Presto Engineering Inc. today announced that it has joined GLOBALSOLUTIONS, GF's ecosystem of partners that provides services from conception to production.

Molex announces acquisition of BittWare

Thu, 5 May 2018
New Hampshire company specializes in high-end FPGA computing platforms designed to improve performance and time-to-revenue for OEMs.

Global, U.S. electronics supply chains see healthy midyear business conditions

Fri, 5 May 2018
The first quarter of this year was very strong globally, with growth across the entire electronics supply chain.

Micron and Intel extend their leadership in 3D NAND flash memory

Mon, 5 May 2018
Micron Technology, Inc. (Nasdaq:MU), and Intel Corporation today announced production and shipment of the industry's first 4bits/cell 3D NAND technology.

Memory device packaging: From leadframe to TSV

Tue, 5 May 2018
Memory devices employ a wide range of packaging technology from wire-bond leadframe and BGA to TSV.

Lumentum orders Veeco MOCVD system

Wed, 5 May 2018
Veeco Instruments Inc. announced that Lumentum Holdings Inc. has ordered the Veeco K475i™Arsenide/Phosphide (As/P) Metal Organic Chemical Vapor Deposition (MOCVD) System for production of its advanced semiconductor components.

Microsemi continues to expand silicon carbide product portfolios

Thu, 5 May 2018
Microsemi Corporation (Nasdaq: MSCC), a provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced it will be expanding its Silicon Carbide (SiC) MOSFET and SiC diode product portfolios early next quarter, including samples of its next-generation 1200-volt (V), 25 mOhm and 80 mOhm SiC MOSFET devices.

Global substrate-like PCB market: Need for miniaturization drives growth

Fri, 5 May 2018
The global substrate-like PCB market will grow at a CAGR of over 7% during the forecast period, according to Technavio analysts.

TowerJazz & Gpixel announce world's smallest global shutter pixel

Tue, 5 May 2018
TowerJazz, the global specialty foundry leader, and Gpixel, Inc., a fast-growing CMOS image sensor (CIS) provider focusing on professional applications, announced today that Gpixel's GMAX0505.

The advanced packaging industry is on the move

Wed, 5 May 2018
Without any doubt, the advanced packaging industry is on the move. Emerging applications are bringing many new challenges. Packaging experts from all over the world are deeply involved in the development of innovative solutions to answer to the market demand dominated by megatrends.

STMicroelectronics announces Executive Committee

Thu, 5 May 2018
New President & CEO Jean-Marc Chery to lead newly formed Executive Committee.

Toshiba Memory Corporation and Synopsys collaborate to accelerate 3D flash memory verification

Fri, 6 Jun 2018
Synopsys, Inc. today announced that it has collaborated with Toshiba Memory Corporation to accelerate the verification of Toshiba Memory Corporation's BiCS FLASH vertically stacked three-dimensional (3D) flash memory.

IEEE Electronics Packaging Society honors heterogeneous integration pioneer and other innovators

Tue, 6 Jun 2018
IEEE, the world's largest technical professional organization dedicated to advancing technology for humanity, and the IEEE Electronics Packaging Society (EPS) today announced Dr. William Chen as the recipient of the 2018 IEEE Electronics Packaging Award.

NXP brings standard packages to RF power

Tue, 6 Jun 2018
New RF power transistors simplify design and manufacturing.

Winbond extends performance of Serial NAND Flash memory with 1Gbit device with maximum data-transfer rate of 83MB/s

Fri, 6 Jun 2018
Winbond’s new high-performance Serial NAND technology also supports a two-chip dual quad interface which gives a maximum data transfer rate of 166MB/s.

pSemi GaN FET driver delivers fast switching to solid-state LiDAR systems

Thu, 6 Jun 2018
pSemi Corporation (formerly known as Peregrine Semiconductor), a Murata company focused on semiconductor integration, announces the availability of the PE29101 gallium nitride (GaN) field-effect transistor (FET) driver for solid-state light detection and ranging (LiDAR) systems.

Micross announces new executive appointment

Fri, 6 Jun 2018
Marshall (Mac) Blythe has joined Micross in the role of General Manager of Component Modification Services (CMS) located in Hatfield, PA.

Imec furthers high-mobility nanowire FETs for nodes beyond 5nm

Tue, 6 Jun 2018
At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the research and innovation hub in nanoelectronics and digital technology presented considerable progress in enabling germanium nanowire pFET devices as a practical solution to extend scaling beyond the 5nm node.

imec presents complementary FET as scaling contender for nodes beyond N3

Wed, 6 Jun 2018
At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the research and innovation hub in nanoelectronics and digital technology, will present a process flow for a complementary FET (CFET) device for nodes beyond N3.

The memory market will grow 40% to US$177 billion in 2018

Thu, 6 Jun 2018
The semiconductor industry posted record results in 2017, with revenue exceeding US$400 billion.

Global organic CMOS image sensor market expected to reach $1,750.0M by 2025

Fri, 6 Jun 2018
The global organic CMOS image sensor market is expected to value at $696.0 million in 2020, and is projected to reach $1,750.0 million by 2025, registering a CAGR of 20.9% from 2021 to 2025.

TowerJazz announces 2018 annual Technical Global Symposium events

Tue, 6 Jun 2018
TowerJazz, the global specialty foundry, today announced details on its 13th annual Technical Global Symposium (TGS) being held in China, Japan, and the United States.

ROHM's new CMOS op-amp delivers leading-class low noise

Thu, 7 Jul 2018
Ideal for industrial applications that demand high-accuracy sensing, including sonar and optical sensors.

Imec demonstrates hybrid finFET-silicon photonics technology for ultra-low power optical I/O

Mon, 7 Jul 2018
Today at its Imec Technology Forum USA in San Francisco, imec, the research and innovation hub in nano-electronics and digital technology, announced that it has demonstrated ultra-low power, high-bandwidth optical transceivers through hybrid integration of Silicon Photonics and FinFET CMOS technologies.

Big changes at the top and bottom of Q1 semiconductor equipment market shares

Mon, 7 Jul 2018
Market shares of semiconductor equipment manufacturers shifted significantly in Q1 2018 as Applied Materials, the top supplier dropped, according to the report “Global Semiconductor Equipment: Markets, Market Shares, Market Forecasts,” recently published by The Information Network.

Optimized stepping for fan-out wafer and panel packaging

Mon, 7 Jul 2018
Optimized stepping, based on parallel analysis of die placement errors and prediction of overlay errors, can increase lithography throughput by more than an order of magnitude and deliver commensurate reductions in cost of ownership. The productivity benefits of optimized stepping are demonstrated using a test reticle with known die placement errors.

High gas flow rates create pumping challenge

Tue, 7 Jul 2018
Increasingly complicated 3D structures such finFETs and 3D NAND require very high aspect ratio etches. This, in turn, calls for higher gas flow rates to improve selectivity and profile control. Higher gas flow rates also mean higher etch rates, which help throughput, and  higher rates of removal for etch byproducts.

The outlook for new metrology approaches

Tue, 7 Jul 2018
To keep up with Moore's Law, the semiconductor industry continues to push the envelope in developing new device architectures containing novel materials.

FET fabrication from fins to nano-sheets

Wed, 7 Jul 2018
As the commercial IC fabrication industry continues to shrink field-effect transistor (FET) sizes, 2D planar structures evolved into 3D fins which are now evolving into 3D stacks of 2D nano-sheets.

Industry overshooting capital spending needs for NAND flash memory

Wed, 7 Jul 2018
Overspending by the major NAND suppliers expected to further cool NAND flash prices this year.

imec shows integrated 5G chip directions

Thu, 7 Jul 2018
To fulfill the promise of the Internet of Things (IoT), the world needs low-cost high-bandwidth radio-frequency (RF) chips for 5th-generation (5G) internet technology.

Micron and Intel announce update to 3D XPoint joint development program

Tue, 7 Jul 2018
Micron and Intel today announced an update to their 3D XPoint joint development partnership, which has resulted in the development of an entirely new class of non-volatile memory with dramatically lower latency and exponentially greater endurance than NAND memory.

Toshiba Memory Corporation develops 96-layer BiCS FLASH with QLC technology

Mon, 7 Jul 2018
Toshiba Memory will start to deliver samples to SSD and SSD controller manufacturers for evaluation from the beginning of September, and expects to start mass production in 2019.

Toshiba Memory Corporation starts construction of the first fabrication facility in Kitakami City, Iwate Prefecture

Tue, 7 Jul 2018
On its completion in autumn 2019, the facility will be one of the most advanced manufacturing operations in the world, dedicated to production of 3D flash memory.

Semiconductor Research Corporation releases $26M in new research funds

Thu, 7 Jul 2018
JUMP program funds 24 new research projects to amplify mission of its six innovation centers.

School district of Osceola County first to deliver SEMI High Tech U program

Thu, 7 Jul 2018
In a key move to inspire the next generation of innovators, the School District of Osceola County (SDOC) today became the first school district to join the SEMI High Tech U (HTU) Certified Partner Program (CPP), a curriculum that prepares high-school students to pursue careers in STEM fields.

Apple's strategy towards 3D sensing is pushing VCSEL industry

Thu, 7 Jul 2018
The VCSEL industry took a strategic turn last year with the release of the latest iPhone. Indeed the leading smartphones manufacturer, Apple revealed to the entire world a new smartphone with innovative 3D sensing function based on VCSEL technology.

Global GDP impact on worldwide IC market growth forecast to rise

Tue, 7 Jul 2018
Correlation coefficient expected to reach a very high level of 0.95 in the 2018-2022 timeframe.

Toshiba develops 40V N-channel power MOSFETs with improved thermal performance

Tue, 7 Jul 2018
New packaging provides double-sided cooling for improved heat dissipation.

Xperi partners with UMC to support production of direct and hybrid bonding 3D semiconductor technologies

Thu, 8 Aug 2018
Partnership enables UMC to develop and manufacture products utilizing Invensas DBI and ZiBond technologies.

Mid-year global semiconductor sales up 20.4% compared to 2017

Mon, 8 Aug 2018
Q2 sales are highest on record, 6.0 percent more than previous quarter, 20.5 percent higher than Q2 of last year.

Achronix and Mentor partner to provide link between high-level synthesis and FPGA technology

Tue, 8 Aug 2018
Achronix Semiconductor Corporation today announced availability of an optimized High-Level Synthesis (HLS) flow from its partner, Mentor, a Siemens business, for its FPGA technology products.

European electronics industry CEOs call on European Commission to bolster sector's competitiveness

Wed, 8 Aug 2018
In a bid to reinvigorate Europe’s electronics strategy and strengthen the region’s position in key emerging technologies, European electronics industry CEOs in June called on public and private actors to accelerate collaboration at the European Union and national levels.

DRAM sales forecast to top $100B this year with 39% market growth

Thu, 8 Aug 2018
With 24% IC marketshare, DRAM expected to account for nearly one in four IC sales dollars spent.

TowerJazz to hold Technical Global Symposium (TGS) in China

Tue, 8 Aug 2018
TowerJazz, the global specialty foundry, announced details of its China Technical Global Symposium (TGS) event in Shanghai on August 22, 2018.

SEMI integration of ESD Alliance underway

Tue, 8 Aug 2018
SEMI today announced that all legal requirements have been met for the ESD (Electronic Systems Design) Alliance to become a SEMI Strategic Association Partner.

Toshiba announces next-generation superjunction power MOSFETs

Mon, 8 Aug 2018
New devices increase power supply efficiency even further.

Soitec and MBDA to acquire Dolphin Integration Assets

Tue, 8 Aug 2018
Soitec (Euronext Paris), a designer and manufacturer of semiconductor materials, and MBDA, announce the joint acquisition of Dolphin Integration.

MRSI Systems launches MRSI-HVM3P for new applications extending the MRSI-HVM3 die bonder family

Tue, 8 Aug 2018
MRSI Systems (Mycronic Group), is expanding its high speed MRSI-HVM3 die bonder platform with the launch of the MRSI-HVM3P to offer configurations for active optical cable (AOC), gold-box packaging, and other applications in addition to chip-on-carrier (CoC).

IDT and Steradian Semiconductors announce strategic partnership

Wed, 8 Aug 2018
Integrated Device Technology, Inc. announced today a strategic partnership with Steradian Semiconductor Pvt. Ltd. to deliver ultra-high resolution 4D mmWave imaging RADAR for emerging industrial, security, medical, and autonomous vehicle markets.

Worldwide semiconductor revenue hit record $120.8B in Q2 2018

Wed, 8 Aug 2018
Samsung Electronics, Intel and SK Hynix continued to lead the semiconductor market in Q2 2018.

Immersion announces appointment of Tom Lacey as interim CEO and board member

Thu, 8 Aug 2018
Lacey succeeds Carl Schlachte, the company’s prior Interim CEO, who is resigning as a director of Immersion.

GlobalFoundries reshapes technology portfolio

Tue, 8 Aug 2018
GLOBALFOUNDRIES today announced an important step in its transformation, continuing the trajectory launched with the appointment of Tom Caulfield as CEO earlier this year. In line with the strategic direction Caulfield has articulated, GF is reshaping its technology portfolio to intensify its focus on delivering truly differentiated offerings for clients in high-growth markets.

Google joins Si2 Board of Directors

Wed, 8 Aug 2018
Election reflects growing influence of vertical integration in IC design.

Memory ICs to account for 53% of total 2018 semi capex

Wed, 8 Aug 2018
Flash memory is forecast to represent the largest share of capital spending while DRAM capex grows at the highest rate this year.

ASMC 2019 Call for Papers deadline is October 9, 2018

Fri, 9 Sep 2018
Educate the industry about the latest in advanced processes and materials.

2019 ECTC abstract submission deadline is October 8

Tue, 9 Sep 2018
This premier international conference, sponsored by the IEEE Electronics Packaging Society (IEEE EPS), covers a wide spectrum of electronic packaging technology topics, including components, materials, assembly, interconnect design, device and system packaging, wafer level packaging, Si photonics, LED and IoT, optoelectronics, 2.5D and 3D integration technology, and reliability.

"Dreams Start Here" at SEMICON Japan 2018 in era of AI

Tue, 9 Sep 2018
Japan is at the heart of the semiconductor industry as the era of artificial intelligence (AI) dawns. SEMICON Japan 2018 will highlight AI and SMART technologies in Japan's industry-leading event.

GOWIN Semiconductor unveils the latest embedded memory products

Mon, 9 Sep 2018
The 2 new embedded FPGA devices were designed with low power, small package size, and low cost in mind. 

Keysight Technologies' 3D planar electromagnetic simulator certified for GLOBALFOUNDRIES 22FDX process technology

Tue, 9 Sep 2018
Keysight Technologies, Inc. (NYSE: KEYS), a technology company that helps enterprises, service providers, and governments accelerate innovation to connect and secure the world, today announced that the company's 3D planar electromagnetic (EM) simulator, Momentum, has been certified for GLOBALFOUNDRIES (GF) 22FDX, 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology.

GLOBALFOUNDRIES extends FinFET offering with new features to enable tomorrow's intelligent systems

Tue, 9 Sep 2018
Feature-rich semiconductor platform delivers competitive performance and scalability for next-generation compute applications.

GLOBALFOUNDRIES delivering 8SW RF SOI client chips on 300mm platform for next-generation mobile applications

Wed, 9 Sep 2018
RF SOI technology builds on manufacturing legacy that reaches new milestone with more than 40 billion chips shipped.

China forecast to account for 90% of pure-play foundry market growth in 2018

Wed, 9 Sep 2018
Driven by cryptocurrency device demand, TSMC's China sales are expected to surge by 79% this year.

JCET Group appoints distinguished semiconductor industry executive Dr. Lee Choon Heung as CEO

Fri, 9 Sep 2018
Dr. Lee brings to JCET a wealth of expertise and veteran leadership with 20 years of extensive semiconductor packaging and test experience.

Synopsys delivers automotive-grade IP in TSMC 7nm process for ADAS designs

Mon, 10 Oct 2018
Synopsys, Inc. today announced delivery of automotive-grade DesignWare Controller and PHY IP for TSMC's 7-nanometer (nm) FinFET process.

CMOS image sensors: Yole Développement is increasing its forecasts again

Thu, 10 Oct 2018
2017 saw aggregated CIS industry revenue of US$13.9 billion. And 5 years later, the consulting company Yole announces more than US$ 23 billion.

Overcoming challenges of futuristic transistor technology below 5nm node

Fri, 10 Oct 2018
To scale down a transistor below a 5nm node is one of the vital concerns for VLSI industry as there are various challenges due to the shrinking of components. Several researches are going on worldwide to overcome the challenges of future technology nodes. Among them, this article reviews the potential transistor structures and materials like Carbon Nano-tube FET, Gate-All-Around FET, and Compound Semiconductors as solutions to overcome the problems of scaling the existing silicon FinFET transistor below 5nm node.

Synopsys Design Platform enabled for TSMC's multi-die 3D-IC advanced packaging technologies

Fri, 10 Oct 2018
Synopsys, Inc. today announced the Synopsys Design Platform fully supports TSMC's wafer-on-wafer (WoW) direct stacking and chip-on-wafer-on-substrate (CoWoS) advanced packaging technologies.

GOWIN Semiconductor's GW1NS family of products named Arm TechCon 2018 Innovation Award finalist for design innovation of the year

Wed, 10 Oct 2018
GOWIN Semiconductor today announced that its GW1NS product family was named a 2018 Arm TechCon Innovation Award finalist for design innovation of the year.

GLOBALFOUNDRIES expands RFwave Partner Program to speed time-to-market for wireless connectivity, radar and 5G

Thu, 10 Oct 2018
GLOBALFOUNDRIES today announced the addition of nine new partners to its growing RFwave Partner Program.

MagnaChip introduces high-voltage super junction MOSFET

Mon, 10 Oct 2018
MagnaChip Semiconductor Corporation, a designer and manufacturer of analog and mixed-signal semiconductor platform solutions, today announced the introduction of a new High-Voltage Super Junction MOSFET with a 900V breakdown voltage and low total gate charge.

Samsung debuts semiconductor innovations at Samsung Tech Day

Fri, 10 Oct 2018
Technologies introduced at the event include 7nm LPP EUV, SmartSSD and 256GB 3DS RDIMM.

Silvaco appoints Babak Taheri as Chief Technology Officer

Mon, 10 Oct 2018
Dr. Taheri will be taking Silvaco’s advanced positions in FinFET and beyond nodes, novel materials, emerging memory and advanced display technologies, to the next level.

Advanced packaging technologies are key for semiconductor innovation

Wed, 10 Oct 2018
In the era of a slowing Moore's Law, advanced packaging has emerged as the savior of future semiconductor development.

Cadence custom/AMS flow certified on Samsung 7LPP process technology

Wed, 10 Oct 2018
Cadence Design Systems, Inc. today announced that its custom and analog/mixed-signal (AMS) IC design tools have achieved certification for Samsung Foundry’s 7nm Low Power Plus (7LPP) process technology.

Global semiconductor sales in September up 13.8% year-to-year

Mon, 10 Oct 2018
Q3 sales are highest on record, 4.1 percent more than previous quarter, 13.8 percent higher than Q3 of last year.

pSemi announces frequency extension and volume production of the 55 GHz Digital Step Attenuator (DSA)

Tue, 10 Oct 2018
This mmWave product is the world's first single-chip silicon-on-insulator (SOI) DSA to support the entire 9 kHz to 55 GHz frequency range.

Innodisk bringing the next-generation NAND flash to the industrial embedded market

Wed, 10 Oct 2018
Innodisk is launching its industrial-grade 3D NAND SSD series, making the newest NAND flash technology available for the challenging requirements of embedded and industrial applications.

Renesas Electronics announces absorption-type merger with consolidated subsidiary

Wed, 10 Oct 2018
Renesas Electronics Corporation today announced that it has resolved at the Meeting of Board of Directors held on October 31, 2018 to consolidate its wholly-owned subsidiary Renesas Semiconductor Package & Test Solutions Co, Ltd.

Semiconductor Research Corporation welcomes SK hynix to its acclaimed GRC and NST research programs

Thu, 11 Nov 2018
SRC research focused on next-generation semiconductor technology continues to attract the world's leading semiconductor design and manufacturing companies.

GLOBALFOUNDRIES, indie Semiconductor deliver performance-enhanced microcontrollers for automotive applications

Mon, 11 Nov 2018
GLOBALFOUNDRIES and indie Semiconductor today announced the release of a new generation of customized microcontrollers on GF's 55nm Low Power Extended (55LPx) automotive-qualified platform, which includes embedded non-volatile memory (SuperFlash) technology.

Micron collaborates with premium German automaker to advance automotive memory technologies

Wed, 11 Nov 2018
Micron Technology, Inc., (Nasdaq: MU) today announced at Electronica 2018 that it will collaborate with the BMW Group to further advance the development of automotive memory solutions used in vehicles.

MIRPHAB offering design, production and business planning for companies developing mid-infrared devices for chemical sensing and spectroscopic applications

Wed, 11 Nov 2018
MIRPHAB, a European Commission project to create a pilot line to fabricate mid-infrared (MIR) sensors by 2020, is accepting proposals from companies that want to develop and prototype new MIR devices that operate in gas-and-liquid media.

Solution for next generation nanochips comes out of thin air

Mon, 11 Nov 2018
The secret ingredient for the next generation of more powerful electronics could be air, according to new research.

MagnaChip to commence volume production of high-voltage IGBT products for power module

Mon, 11 Nov 2018
MagnaChip Semiconductor announced that volume production has commenced for an IGBT product for power module targeted to high-voltage industrial applications.

New quantum materials could take computing devices beyond the semiconductor era

Mon, 12 Dec 2018
Mutliferroics are promising candidates for new type of memory and logic circuits.

CEA-Leti moves 3D sequential integration closer to commercialization

Tue, 12 Dec 2018
Leti, a research institute at CEA Tech, has reported breakthroughs in six 3D-sequential-integration process steps that previously were considered showstoppers in terms of manufacturability, reliability, performance or cost.

Synopsys and imec demonstrate accelerated modeling of complementary FET (CFET) technology

Mon, 12 Dec 2018
Synopsys, Inc. announced today another milestone in its longstanding partnership with imec.

Lattice Semiconductor appoints Glenn O'Rourke as Corporate VP, Global Operations

Tue, 12 Dec 2018
Lattice Semiconductor Corporation announced the appointment of Glenn O’Rourke as the Company’s Corporate Vice President, Global Operations, effective immediately.

Assessing the promise of gallium oxide as an ultrawide bandgap semiconductor

Tue, 12 Dec 2018
Researchers at the University of Florida, the U.S. Naval Research Laboratory and Korea University provide a detailed perspective on the properties, capabilities, current limitations and future developments for one of the most promising UWB compounds, gallium oxide.

Advanced testing paradigm shifting in era of heterogeneous integration

Mon, 1 Jan 2019
SEMI Taiwan Testing Committee founded to strengthen the last line of defense to ensure the reliability of advanced semiconductor applications.

Rambus acquires memory technology assets of Diablo Technologies

Thu, 1 Jan 2019
Rambus Inc. today announced it has acquired the assets of Diablo Technologies to broaden its portfolio in the hybrid DRAM and Flash memory markets.

Value of semiconductor mergers and acquisitions falls considerably

Thu, 1 Jan 2019
2018 semiconductor M&A valued at $23.2 billion, down from the record $107.3 billion in 2015.

ZEISS launches new high-resolution 3D X-ray imaging solutions

Wed, 1 Jan 2019
ZEISS today unveiled a new suite of high-resolution 3D X-ray imaging solutions for failure analysis (FA) of advanced semiconductor packages, including 2.5/3D and fan-out wafer-level packages.

Fan-out system-in-board technology: Enabling RF and processor module and system-level integration

Wed, 1 Jan 2019
SEMI met with Martin Schrems, director of Strategy and Business Development at AT&S AG, to discuss Fan-Out technology trends ahead of SEMI 3D & Systems Summitin Dresden, Germany.

SEMI 3D & Systems Summit showcases heterogeneous 3D integration

Wed, 1 Jan 2019
Inaugural summit offers latest insights in semiconductor manufacturing and applications.

Semiconductor R&D spending will step up after slowing

Fri, 2 Feb 2019
3D die-stacking technologies, manufacturing barriers, and growing complexities in end-use systems among the technical challenges that are expected to lift R&D growth rates through 2023.

KLA-Tencor appoints Victor Peng to Board of Directors

Fri, 2 Feb 2019
KLA Corporation today announced the appointment of Victor Peng to its board of directors.

Who is leading the RF GaN IP landscape?

Wed, 2 Feb 2019
The RF GaN industry is showing an impressive growth with a 23% CAGR between 2017 and 2023, driven by telecom and defense applications. By the end of 2017, the total RF GaN market was close to US$380 million and 2023 should reach more than US$1.3 billion with an evolving industrial landscape.

Advanced packaging: At the heart of innovation

Thu, 2 Feb 2019
The semiconductor industry showed impressive figures in 2017: +21.6% YoY growth to reach about US$ 412 billion.

Cadence selected as primary EDA tool vendor by GLOBALFOUNDRIES

Fri, 2 Feb 2019
Cadence Design Systems, Inc. today announced that GLOBALFOUNDRIES (GF) has chosen Cadence as the primary EDA tool vendor for use in Avera Semi, a GF subsidiary, for advanced node chip design projects.

eSilicon builds momentum as a strong tier one FinFET ASIC supplier

Fri, 2 Feb 2019
eSilicon, a provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the achievement of multiple milestones related to the company's growth in the tier one FinFET ASIC market, serving high-bandwidth networking, high-performance computing, AI and 5G infrastructure.

GlobalFoundries and Dolphin Integration to deliver differentiated FD-SOI adaptive body bias solutions

Tue, 2 Feb 2019
IP to accelerate energy-efficient SoC designs and push the boundaries of single-chip integration.

CEA-Leti and Stanford target edge-AI apps with breakthrough NVM memory cell

Wed, 2 Feb 2019
Researchers at CEA-Leti and Stanford University have developed the world’s first circuit integrating multiple-bit non-volatile memory (NVM) technology called Resistive RAM (RRAM) with silicon computing units, as well as new memory resiliency features that provide 2.3-times the capacity of existing RRAM.

Rice U. researchers unveil Internet of Things security feature

Wed, 2 Feb 2019
'Physically unclonable function' is 10 times more reliable than previous methods.

Synopsys and GLOBALFOUNDRIES collaborate to develop industry's first automotive grade 1 IP for 22FDX process

Thu, 2 Feb 2019
Synopsys, Inc. and GLOBALFOUNDRIES today announced a collaboration to develop a portfolio of automotive Grade 1 temperature DesignWare Foundation, Analog, and Interface IP for the GF 22-nm Fully-Depleted Silicon-On-Insulator process.

GOWIN Semiconductor announces release of the new GOWIN EDA tools for improved performance on new FPGA product families

Fri, 2 Feb 2019
GOWIN Semiconductor Corp. announces the release of GOWIN's new EDA tool, YunYuan 1.9.

Soitec joins China Mobile 5G Innovation Center

Mon, 2 Feb 2019
Soitec, a designer and manufacturer of innovative semiconductor materials, today announced it is the first materials supplier to join the China Mobile 5G Innovation Center.

Cadence CMP Process Optimizer enables Toshiba Memory to accelerate delivery of advanced 3D Flash memory devices

Mon, 2 Feb 2019
Cadence Design Systems, Inc. today announced that Toshiba Memory Corporation has successfully used the Cadence CMP Process Optimizer, a model calibration and prediction tool that accurately simulates multi-layer thickness and topography variability for the entire layer stack, to accelerate the delivery of its advanced 3D flash memory devices.

Nominations open for ESD Alliance Governing Council

Tue, 2 Feb 2019
The Electronic System Design Alliance, a SEMI Strategic Association Partner, today opened nominations for member company executives to serve on the ESD Alliance Governing Council for the next two-year term.

Introducing Semiconductor Digest

Tue, 4 Apr 2019
Semiconductor Digest is a new magazine dedicated to the worldwide semiconductor industry