Topic Index

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0-9

SMC 2012: Supply chain opportunities in OLEDs, energy storage, and power semiconductors

Fri, 11 Nov 2012

Materials experts from across the supply chain gathered at the 2012 Strategic Materials Conference 2012 in San Jose in October, discussing key materials needs for micromanufacturing outside the CMOS mainstream: OLEDs and GaN-on-silicon power semiconductors, graphene, CNTs, and self-assembling polymers.

Process Watch: A clean, well-lighted reticle

Fri, 10 Oct 2012

In the fifth installment in a series called Process Watch, the authors discuss the need for proper reticle cleaning and inspection. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.

European consortia, ASML, supplier network plan for 450mm transition

Thu, 10 Oct 2012

At SEMICON Europa, European government representatives, consortia, and suppliers discussed programs to support and participate in the 450mm wafer-size transition -- including a comprehensive presentation from ASML about its roadmap for 450mm EUV platforms.

Process Watch: Cycle time’s paradoxical relationship to inspection

Tue, 12 Dec 2012

In the seventh installment in a series called Process Watch, the authors discuss cycle time and the impact of inspection. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.

Nikon and Intel announcements highlight 450mm news from Japan

Thu, 12 Dec 2012

In news from Semicon Japan, a Nikon spokesperson said that the company plans to ship high-volume manufacturing (HVM) lithography tools in 2017, and Intel officially announced a 450mm Japan Metrology Center.

Process Watch: Breaking parametric correlation

Tue, 11 Nov 2012

In the sixth installment in a series called Process Watch, the authors discuss the ins and outs of parametric correlation when using measurements based on reflectometry, ellipsometry, or a combination of the two. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.

Process Watch: Bigger and better wafers

Thu, 8 Aug 2012

In the third installment in a series called Process Watch, the authors discuss some of the challenges of 450mm wafers. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.

Process Watch: The dangerous disappearing defect

Tue, 5 May 2012

In this first installment of a series called "Process Watch,” experts from KLA-Tencor explain why a defect might be classified as “Not Found” or “SEM Non-visual (SNV),” and how a SNV count can disguise or hide real problems.

Process Watch: Skewing the defect pareto

Mon, 6 Jun 2012

In the second installment in a series called Process Watch, the author provides tips on how to make sure you’re reviewing the yield killing defects and not wasting time reviewing nuisance events. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions for chip manufacturing at the leading edge.

Waiting for the next "golden year"

Fri, 9 Sep 2012

While various industry segments appear to be tapping the brakes, others are revving their engines, observes SEMI's Christian Gregor Dieseldorff -- and a 2012 stall could pave the way for a record-breaking 2013.

Supply chain readiness in an era of accelerated change

Fri, 8 Aug 2012

In this SEMI News and Views blog, Karen Savala covers EUV lithography, 450mm wafers, and 3D IC developments, based on her recent presentation at SEMICON West, “Supply Chain Readiness in an Era of Accelerated Change.”

Dynamic changes impacting advanced electronic materials industry

Wed, 8 Aug 2012

Learn about the changes in semiconductor manufacturing as well as related markets -- photovoltaics, displays, LEDs, etc -- at the 2012 Strategic Materials Conference (SMC), to be held on October 23-24 in San Jose, CA. SEMI reports.

Japan's semiconductor industry: Fabs, equipment, and materials

Wed, 10 Oct 2012

Even though semiconductor manufacturers in Japan are consolidating and transitioning to a "fab-lite" strategy,  the region still represents a large installed fab capacity and a major market for equipment and materials suppliers.

Process Watch: Taming the overlay beast

Tue, 9 Sep 2012

In the fourth installment in a series called Process Watch, the authors discuss overlay registration and new capabilities to align to buried layers. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.

TSMC's schedule for 450mm mass production -- and lithography is the key

Wed, 9 Sep 2012

During sessions at this month's SEMICON Taiwan, execs from TEL, Lam Research, Applied Materials and KLA-Tencor revealed the latest developments in 450mm technology.

Blog: Bring me the rhinoceros: A Review of the 2013 SPIE Advanced Lithography EUVL Conference

Thu, 3 Mar 2013

The 2013 SPIE Advanced Lithography EUVL Conference started with many of us looking forward to Sam Sivakumar's kickoff presentation on results from Intel’s EUVL pilot line.

Blog: Further comments on physics and engineering of EUV sources

Thu, 3 Mar 2013

Dr. Vivek Bakshi blogs about EUV Lithography (EUVL) and related topics of interest. He has edited two books on EUVL and is an internationally recognized expert on EUV Source Technology and EUV Lithography. He consults, writes, teaches and organizes EUVL related workshops.

Blog: EUV source roadmaps: Physics vs Engineering

Thu, 3 Mar 2013

I am frequently asked by my consulting clients and colleagues when EUV sources will be ready to support high volume manufacturing (HVM) of semiconductors. It is a difficult question to answer, partly because readiness metrics have been a moving target, or the latest performance data is not very clear. For example, how many wafers per hour will make it cost-effective to adopt EUVL over the alternatives of triple or quadruple 193 nm immersion lithography for a given  product at a specified feature size for 300 mm or 450 mm wafers? Is the latest data in pulse mode and integrated, and for how long an operation?

Blog: Doing more with Moore’s Law: Status report from 2012 Source Workshop

Thu, 3 Mar 2013

The 2012 Source Workshop was held Oct. 8-11 in Dublin, Ireland, in the Clinton Auditorium on the campus of University College Dublin. This is the industry's largest annual gathering of EUV and soft X-ray source experts, who took the opportunity to discuss the latest results from their labs.

MEMS New Product Development Blog: The technology development process and design review checklist

Tue, 5 May 2013

After a functional A-sample prototype is built, it doesn't take long for a project to gain traction that has market pull.  This is usually the point that a project becomes highly visible within a company and it enters the Technology Development Process (TDP).

RRAM: Understanding reliability issues

Thu, 2 Feb 2013

Tim Turner, the Reliability Center Business Development Manager at the College of Nanoscale Science and Engineering (CNSE), Albany, NY, blogs about the potential of resistive memory and the reliability challenges the must be overcome.

Opinion: MEMS new product development: The first prototype

Mon, 2 Feb 2013

In the second article of the MEMS new product development blog, the importance of the first prototype will be discussed.

Looking for an integrated post-tapeout flow

Wed, 2 Feb 2013

Dr. Steffen Schulz discusses the role of a flexible platform for computational lithography in a successful business strategy.

Opinion: MEMS new product development, a sellable plan

Wed, 1 Jan 2013

In David DiPaola's blog, he discuss the critical factors needed for success in the early stage of new MEMS product development.

The gleam of well-polished sapphire

Tue, 1 Jan 2013

Is it time for high-brightness LED manufacturing to get serious about process control?  If so, what lessons can be learned from traditional, silicon-based integrated circuit manufacturing?

Innovations in computational lithography for 20nm

Tue, 1 Jan 2013

Several innovations in computational lithography have been developed in order to squeeze every possible process margin out of the lithography/patterning process.  In this blog, Gandharv Bhatara of Mentor Graphicsl talks about two specific advances that are currently in deployment at 20nm.

Process Watch: Exploring the dark side

Fri, 1 Jan 2013

A particle as small as three microns in diameter, attached to the back side of the wafer—the dark side, if you will—can cause yield-limiting defects on the front side of the wafer during patterning of a critical layer.

DFM Services in the Cloud

Wed, 2 Feb 2013

Joe Kwan is the Product Marketing Manager for Calibre LFD and DFM Services at Mentor Graphics. He is also responsible for the management of Mentor’s Foundry Programs. He previously worked at VLSI Technology, COMPASS Design Automation, and Virtual Silicon. Joe received a BA in Computer Science from the University of California Berkeley and an MS in Electrical Engineering from Stanford University.

MEMS new product development, critical design and process steps for successful prototypes (Part 1)

Fri, 3 Mar 2013

In the third article of the MEMS new product development blog, critical design and process steps that lead to successful prototypes will be discussed.

Blog: Moving forward with Moore’s Law: Throughput of EUVL scanners

Thu, 3 Mar 2013

In order to bring EUVL scanners into high volume manufacturing (HVM) of computer chips, its throughput of 10 wafers per hour (WPH) needs to increase. That brings up three questions: how much do we need to increase the current throughput for HVM insertion, what needs to be done to increase throughput, and how quickly can this increase be achieved?

MEMS New Product Development Blog: Critical design and process steps for successful prototypes Part 2

Mon, 4 Apr 2013

The fourth article of the MEMS new product development blog is Part 2 of the critical design and process steps that lead to successful prototypes.  In the last article, the discussion focused on definition of the customer specification, product research, a solid model and engineering analysis to validate the design direction.  The continuation of this article reviews tolerance stacks, DFMEA, manufacturing assessment and process mapping.  

IFTLE 139 More on Apple A7 processor Production Rumors; DARPAs ICECool part 2 – Applications

Mon, 3 Mar 2013

Steve Shen of Digitimes reports that TSMC is expected to tape out Apple's A7 processor on a 20nm process in March and then “...move the chip into risk production in May-June, which will pave the way for commercial shipments in the first quarter of 2014… TSMC will utilize 14-fab to manufacture the A7 chips for Apple.”

The secrets of 14nm lithography

Thu, 3 Mar 2013

The long-expected demise of optical lithography for manufacturing ICs has been delayed again, even though the technology itself has reached a plateau with a numerical aperture of 1.35 and an exposure wavelength of 193nm. Immersion lithography is planned for the 20/22nm node, and with the continued delay of EUV, is now the plan of record for 14nm.

Reducing mask write-time—which strategy is best?

Tue, 10 Oct 2013
An upcoming challenge of advanced-node design is the expected mask write time increase associated with the continued use of 193nm wavelength lithography.

3D-IC: Two for one

Wed, 9 Sep 2013
Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about upcoming events related to 3D ICs.

Rebirth of mask process correction for better wafer lithography

Wed, 7 Jul 2013

Who knew that mask process correction (MPC) would again become necessary for the manufacturing of deep ultraviolet (DUV) photomasks?

MEMS New Product Development: The importance of product validation

Wed, 7 Jul 2013

Product validation is an essential part of all successful MEMS new product developments. It is the process of testing products under various environmental, mechanical or electrical conditions to simulate life in an accelerated manner.

Blog Review October 14 2013

Mon, 10 Oct 2013
Recent blogs address semiconductors in healthcare (blood cell sorters), FinFETs and logic roadmaps, 450mm progress, panel level embedded tech, materials innovation, options to reduce mask write time, SOI and EUV.

Model-based hints: GPS for LFD success

Wed, 10 Oct 2013
For several technology nodes now, designers have been required to run lithography-friendly design (LFD) checks prior to tape out and acceptance by the foundry. Due to resolution enhancement technology (RET) limitations at advanced nodes, we are seeing significantly more manufacturing issues, even in DRC-clean designs.

Scaling makes monolithic 3D IC practical

Mon, 10 Oct 2013
In the 1960s, James Early of Bell Labs proposed three-dimensional structures as a natural evolution for integrated circuits. Since then many attempts have been made to develop such a technology.

Monte Carlo analysis has become a gamble

Mon, 10 Oct 2013
Dr. Bruce McGaughy, CTO and SVP of Engineering at ProPlus Design Solutions, Inc. blogs about the wisdom of Monte Carlo analysis when high sigma methods are perhaps better suited to today’s designs.

Are we using Moore's name in vain?

Tue, 11 Nov 2013
Clearly Moore's law is about cost, and Gordon Moore’s observation was that the optimum number of components (nowadays - transistors) to achieve minimum cost will double every year.

Celebrating 20 years of BSIM3v3 SPICE models

Thu, 12 Dec 2013
Zhihong Liu of ProPlus Designs reflects on the history of the MOSFET SPICE model called BSIM3.

Paradigm shift: Semi equipment tells the future

Mon, 1 Jan 2014
Looking at the semi-equipment booking should be the first step in any attempt to assess future semiconductor trends.

SEMI ISS: Scaling innovation

Mon, 2 Feb 2014
Ira Feldman blogs about the recent 2014 SEMI Industry Strategy Symposium (ISS).

Long live FinFET

Mon, 2 Feb 2014
Zhihong Liu, Executive Chairman, ProPlus Design Solutions, Inc., San Jose, Calif. blogs on how the industry's move to FinFETs is impacting design.

Plug-and-play test strategy for 3D ICs

Tue, 3 Mar 2014
Three-dimensional (3D) ICs, chips assembled from multiple vertically stacked die, are coming. They offer better performance, reduced power, and improved yield.

Process Watch: Time is the enemy of profitability

Thu, 5 May 2015
There are three main phases to semiconductor manufacturing: research and development (R&D), ramp, and high volume manufacturing (HVM). All of them are expensive and time is a critical element in all three phases.

Solid State Technology announces expanded conference for The ConFab 2017

Wed, 9 Sep 2016
The conference and networking event, will be held at the iconic Hotel del Coronado in San Diego on May 14-17, 2017.

Process Watch: Having confidence in your confidence level

Thu, 4 Apr 2017
This new series of articles highlights additional trends in process control, including successful implementation strategies and the benefits for IC manufacturing.

Process Watch: Hitback analysis improves defect visibility

Tue, 12 Dec 2016
In order to maximize the profitability of an IC manufacturer’s new process node or product introduction, an early and fast yield ramp is required. Key to achieving this rapid yield ramp is the ability to provide quality and actionable data to the engineers making decisions on process quality and needed improvements.

Process Watch: Salami slicing your yield

Mon, 9 Sep 2016
The Process Watch series explores key concepts about process control -- defect inspection and metrology -- for the semiconductor industry. This new series of articles highlights additional trends in process control, including successful implementation strategies and the benefits for IC manufacturing.

Process Watch: Yield management turns green

Mon, 4 Apr 2016
As we celebrate Earth Day 2016, we commend the efforts of companies who have found ways to reduce their environmental impact.