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IFTLE 301 Are Silicon Circuit Boards in our Future?

By Dr. Phil Garrou, Contributing Editor

In IFTLE 300, we commented that the imminent end to scaling will force changes in how we approach the development of new integrated circuits and systems.

IyerSubramanian Iyer, ex IBM fellow, retired from IBM when the chip business was sold off to Global Foundries. He is now the Distinguished Chancellor’s Professor in the EE Dept. at UCLA and Director of the Center of Heterogeneous Integration and Performance Scaling (or CHIPS for short). The CHIPS mission is to interpret and implement Moore’s Law to include all aspects of heterogeneous systems and develop architectures, methodologies, designs, components, materials and manufacturable integration schemes that will shrink system footprint and improve power and performance. Let’s look at his concept of for where the industry should be going.

In the July 2016 issue of IEEE Trans on CPMT, Iyer put pen to paper ( or should we say “fingers to keyboard”) and has laid out the master plan for CHIPS in his article “Heterogeneous Integration for Performance and Scaling.”

Iyer contends that Moore’s law has so far relied on the aggressive scaling of CMOS silicon features. This in turn resulted in a dynamic system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. While scaling on chip has increased >1000X, the integration of multiple dies on packages and boards has scaled by a factor of 3 – 5X. The current slowing of semiconductor scaling [discussed in IFTLE 300] will bring a focus on heterogeneous integration and system-level scaling. This transformation is already under way with 3-D stacking of dies and will evolve to make heterogeneous integration the backbone of sustaining Moore’s law in the years ahead.

While the SoC approach has moved us forwards, a single chip does not make a system. In order to build a system, multiple chips such as processors, memory chips, field programmable gate arrays (FPGAs), transceivers, power regulators, and so on need to be interconnected. Traditionally, this has been done using a printed circuit board (PCB).

Chips are typically packaged before being mounted on the board. While it is true that the package connects the chip to the rest of the system, it does so very inefficiently. For instance, contacted gate pitches in the 14-nm node are about 40 nm, through the hierarchical wiring system, we increase that pitch up step-by-step until, at the upper most wiring level, it is a few micrometers. The C4 bumps then increase this pitch to about 150 μm. The BGA connections to the board take this further to 400 – 600 μm. In essence, to connect two chips the interconnections of chip 1 must fan out to a PCB board pitch and then fan back in to chip 2 pitch , thus causing the inefficiency . Silicon has scaled by over a factor of 1000 in the last 50 years, while packages and boards have scaled by at most a factor of 5.

Iyer contends that with increasing demands on the BW between the chips and the inability to increase the number of physical connections between the chips, serial links need to operate individually at higher and higher data rates. These higher rates mean higher frequency signals carried by the traces on the board and significantly larger noise levels and cross talk between adjacent channels. Consequences of this include:

1) The power to transmit higher frequency signals through SerDes goes up exponentially with data rate.

2) The SerDes circuits themselves become more complex to design and take up more area. modern SoCs may sometime devote almost 25% of their area to SerDes, and in some cases, an even greater fraction of chip power is allocated to SerDes function.

Approaches to System Scaling and Heterogeneous Integration

Iyer proposes Eliminating the Package and directly bonding multiple bare dies to an interconnect fabric (IF) made of silicon. He notes that the first steps in this direction have been silicon interposers but argues that this is not the ultimate solution since an interposer adds cost and complexity by adding an extra level to the overall package. What Iyer is proposing is “to go a step further and transform the interposer into the board”.

He proposes replacing the current epoxy glass PWB board with silicon. This silicon board would be a wafer on which have been processed several levels of fine pitch wiring with the top-most wiring level matching the top chip wire levels with landing pads of similar dimensions that can connect to other die that have been attached with precision alignment (0.5-μm overlay). He calls this wafer the silicon interconnect fabric (Si-IF). Electrical connections between the rigid flat die and the Si-IF will be made by thermal compression bonding. While technology at this fine scale is not available today, Iyer believes it possible in the near future. He believes that two features of this approach make it feasible:

1) the use of small die (a few millimeters on a side)

2) the fact that both the die and IF are made of relatively thick silicon, are flat and have matched CTEs.

Iyer contends that computing is evolving to a more heterogeneous architecture with a combination of special purpose processors, accelerators, and FPGAs which make this Si-IF integration scheme very attractive, since one can synthesize such systems from a variety of off-the-shelf components. In the case of mobile systems and the so-called IoT, heterogeneity is the key requirement. One can integrate analog components, sensors, MEMS, batteries, supercapacitors, and so on as needed. Overall, they expect that this approach will allow significant reduction in overall board footprint.

Iyer has listed the following requirements for such technology to come to pass.

1) Integrated Design System: Today, chips, packages, and boards are all designed separately and almost independently. This will need to become a lot more integrated. In addition, while, today, we do electrical, thermal, and mechanical design more or less independently, these three views of the system will also have been integrated.

Such a system will require significantly more understanding of the interactions between these 3 views and the development of a significantly more sophisticated set of tools.

2) New Design for Test and Repair Methodologies: As rework is no longer an option, and die-level testing will be limited in scope, the component chips will have to test themselves to a large extent. While technologies to do this exist, they will need to be adapted to bare die.

3) Interface Standardization: Our approach allows us to have a large number of inter die connections and this allows us to parallelize the connections and have simpler interfaces. However, this approach needs to be adopted universally. We believe that the standardization of slower and easier to build parallel interfaces is more easily achieved than serial interfaces.

4) Power Delivery and Thermal Management: In the case of high-end systems, one would need to deliver ∼1 kW of power at different voltages. This will require integrated power management techniques, and the use of features, such as Hi-Q inductors, buck convertors, and power switches, than can either be components attached to the IF or integrated into the Si-IF. Removing the generated heat is another challenge. One mitigating factor in the use of the Si-IF is that the silicon itself is a good thermal conductor and can be an integral part of the heat-sinking solution. The die themselves may have integrated heat sinks made, for example, with silicon fluidic channels or micro machined fins.

5) Structural Properties of Silicon: While the ability to process silicon as an IF is second to none, care must be exercised in wafer handling. Fortunately, silicon-processing equipment has evolved to accommodate this

6) Cost: It has been argued that silicon is expensive and organic materials would be more cost effective. If we need fine pitch interconnects, then in practice, material cost will be about 10% of the finished product cost. Processing the fine pitch interconnects dominates the cost. In fact, it will be very expensive to fabricate fine pitch (sub-10-μm pitch) interconnects on organic

substrates; while fully depreciated silicon fabs can do this easily and more cost effectively on silicon. There are additional benefits of silicon, such as integrated passives and active IFs. The silicon solar cell substrate suppliers have developed the so-called metallurgical grade Si that is cost competitive.

While the challenges are enormous, so too are the payoffs. When compared with the challenges and costs of continuing to shrink minimum features on a die, he believes “… the value proposition of what we have proposed here is solid”.

 

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8 thoughts on “IFTLE 301 Are Silicon Circuit Boards in our Future?

  1. Scott Jacobs

    It was called Silicon-on-Silicon back in the 1980’s. It was proposed at IBM East Fishkill as a means of increasing the net BiPolar circuit densities for the old mainframes. Any number of studies showed that this was far from an ideal solution and the drawbacks were well known back then. Advanced low-cost, high density interconnect MCMs would have been the way to go with this but BiPolar was dropped in favor of continual integration of CMOS. There were advanced MCM designs back then that are still state-of -the -art today that were never used (and no, I’m not talking astronomically expensive ceramic TCMs). There were thin-film MCM interconnect solutions with massive I/O capabilities that almost looked like wafer-scale integration from a designers ability to interconnect but with superior longer range wiring capabilities – and they were cost-effective. Now that CMOS has run out of scaling steam it would seem that history is repeating itself by starting the next generation interconnect argument with Silicon-on-Silicon – welcome back to the future of 1985.

    Reply
  2. Stan Drobac

    It will indeed be interesting to see if silicon circuit boards are in our future. They are certainly in our past. As you (Phil) surely remember, Silicon Valley startup nChip produced what were then called multi-chip modules by using a silicon circuit board supporting bare die back in the 1990s. The details were different, of course, than what Prof. Iyer is proposing, but the rationale and concept were much the same. nChip was, perhaps, ahead of its time – die quality and other issues limited the success of the technology back then. Here’s hoping that it lives up to its promise this time around.

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  3. John Barnes

    What would be more practical and upgradable would be to have the chips talk with laser or microwaves. The chips would only have power applied with wires and everything else happens wirelessly. The entire assembly is contained in a RF plenum to keep out outside signals. This enhances reliability, reparability and upgradability. Etching anything in stone (or silicon) will create more E-waste and premature obsolesce. Not the best scenario for the use or the environment, unless, those ideas are not the goal.

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  4. Jim Ford

    I feel the pain of silicon feature shrinkage, while PCB’s cannot keep up, every day! Since I design the PCB’s for testing the IC’s at Broadcom Ltd, it is very obvious to me that the packaging technology has an increasingly difficult task bridging the IC and PCB domains. And I agree with Iyer that the best package is no package. None of us knows how this will all play out, but things are going to have to change because we are at a breaking point.

    Reply
  5. Dr. Dev Gupta

    “oracles” from these ex IBM people need to be taken with a large pinch of salt. when at IBM they could not muster support from their own management to take their research interest into production, case in point 3d die stacking with TSVs. Instead they misled the general industry into wrong directions — had the poor OSATs waste resource and time. After burning their fingers with Si interposers OSATs have come back to their senses with SWIFT, SLIM etc. Intel’s EMIB ( already in use even for FPGAs with very high I/O density ) is a direct refutation of this “whole Si circuit board” nonsense ( which if I remember right was already being used by AT&T for MCMs as long ago as the mid ’90s ). These flotsam and jetsam from IBM are conditioned by IBM choices of long ago ( TCM era ) re: conservative die partitioning strategy forced by their own yield issues. And now they don’t even have a Fab. They do not seem to understand that integration at the package / substrate level will remain an interim solution even after the demise of Moore’s Law or the advent of heterogeneous integration, Even in this new era I/O density for the non IBM world ( maintain yield > 95 % with over 50 billion plus leading node transistors on a single chip ) will remain very localized and approaches like EMIB embedded in a Organic substrate ( soon 5 um L/S ) will remain the choice of the vast majority of applications including Supercomputers

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  6. Scott Jacobs

    Read what I said a little closer Dev. I didn’t say IBM had it right back then. IBM did get it wrong just as you noted. That’s precisely why I left IBM in the mid 80’s: they were bungling just about everything back then, including packaging so the writing was all over the wall. But that doesn’t mean there weren’t smart solutions available both, 1) internal to IBM that were never supported by IBM management and 2) outside of IBM in a few defunct MCM companies in Silicon Valley that couldn’t get any serious support from the VCs. My main point was that silicon substrates were a non-ideal solution to swallow back then and if they are being proposed now I could readily think of several better ways to go that are nearly 30 years old now that were developed within IBM but never supported and at a few MCM companies that were never put into full production due to lack of management and/or VC support at the time.

    Reply
    1. Dr. Dev Gupta

      Scott : my comments were not aimed at your post, in fact it did not even appear on this thread when I posted mine ! but you will perhaps agree that IBM still casts a long shadow, though perhaps for not too long as it now out of the Fab business, In a curious reversal of role someone from Yorktown Ht.s came around last month to talk about something key to 3d die stacking that we at Motorola had invented and put into volume production about 20 years ago – first for GaAs PAs w/o which there would be no streamed video in Smart Phones today !

      Reply

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